Abstract The credit card is precoded in binary code representing several digits and has a locator indicator to insure that the card is correctly positioned when inserted in the console or read-out station. The card coding includes the method of arranging high dielectric constant spots or discs and low dielectric constant spots or discs in several groupings related to a plurality of identification digits. The circuitry for reading the encoded data on the credit card includes a capacitive voltage divider to reduce the effect of parasitic capacitance. Additionally, a relatively high voltage level sensing circuit is used to reduce the possibility of error due to oxide film, dirt, high resistance film or the like on the encoded spots.
A circuit for sensing the time constant of separate indicia of relatively high and relatively low dielectric constant mounted in a card in a predetermined pattern and providing an output signal, said sensing circuit comprising: a pulse source; a diode placed in series with said indicia and said pulse source during reading; a capacitor of substantially greater capacitance value than said low dielectric constant but of substantially smaller capacitance than said high dielectric constant indicia connected to said diode for charging it; a resistor connected in the discharge path of said capacitor; and a transistor having its base connected to said resistor for triggering it to provide the output signal responsive to the dielectric constant of said indicia.
Claim 2
Dependent Claim
118 words
A circuit for sensing the time constant of separate indicia of relatively high and relatively low dielectric constant mounted in a card in a predetermined pattern and providing an output signal, said sensing circuit comprising: a pulse source; a diode placed in series with said indicia and said pulse source during reading; a capacitor of substantially greater capacitance value than said low dielectric constant but of substantially smaller capacitance than said high dielectric constant indicia connected to said diode for charging it; a resistor connected in the discharge path of said capacitor; and a transistor having its base connected to said resistor for triggering it to provide the output signal responsive to the dielectric constant of said indicia.
Claim 3
Dependent Claim
37 words
The combination as set forth in claim 1 wherein a plurality of said diodes are all connected to a common terminal of said capacitor to provide for sensing of like bits in the pattern in said card.
Claim 4
Dependent Claim
57 words
The combination as set forth in claim 1 wherein said resistor comprises a first resistor of relatively large magnitude with the base of said transistor and a second resistor of lower magnitude coupled between said first resistor and ground, thus forming a resistor voltage divider to adapt the capacitor voltage divider output to the transistor switching level.
Claim 5
Dependent Claim
31 words
The combination as set forth in claim 1 wherein said transistor is of the NPN type and a diode is connected intermediate its base and the discharge path of said capacitor.
Claim 6
Dependent Claim
89 words
A driver circuit for providing a train of pulses for sensing for the presence and absence of high dielectric constant indicia mounted in a card, comprising: a source of pulses; means for activating the source responsive to positioning of the card in a read position; and a transistor having its control terminal connected to said pulses and having one of its output terminals connectible to one of the indicia for providing a scanning pulse thereto, said transistor operable to provide the scanning pulse at a relatively high voltage level.
Claim 7
Dependent Claim
89 words
A driver circuit for providing a train of pulses for sensing for the presence and absence of high dielectric constant indicia mounted in a card, comprising: a source of pulses; means for activating the source responsive to positioning of the card in a read position; and a transistor having its control terminal connected to said pulses and having one of its output terminals connectible to one of the indicia for providing a scanning pulse thereto, said transistor operable to provide the scanning pulse at a relatively high voltage level.
Claim 8
Dependent Claim
20 words
The combination as set forth in claim 5 in which the voltage level is of the order of 150 volts.