Fast acquisition circuit for a phase locked loop

Claim 1

In a phase locked loop (PLL) of the type having an acquisition mode and a locked mode of operation and including a phase comparator, a loop filter and a voltage controlled oscillator (VCO); said phase comparator being responsive to a reference signal and an output signal of sand VCO, and generating an output signal indicative of phase and frequency differences between said reference signal and VCO output signal; said loop filter being responsive to said phase comparator output signals and providing a control signal for said VCO; said phase comparator generating spurious voltage spikes during said locked mode of PLL operation; said loop filter comprising: first filter means responsive to said phase comparator output signal for providing said PLL with a first predetermined bandwidth during said locked mode of PLL operation; second filter means, responsive to said phase comparator output signal, for filtering said voltage spikes to ground during said locked mode of operation; and interconnecting means, coupled between said first and second filter means, for electrically interconnecting said first and second filter means only during said acquisition mode of PLL operation, to provide thereby said PLL with a second predetermined bandwidth during acquisition mode of PLL operation; the improvement wherein: said first filter means comprises first and second resistors and said first capacitor, each having two terminals, said first resistor being connected at one terminal to said input terminal and the other terminal to one terminal of said second resistor, the other terminal of said second resistor being connected to one terminal of said first capacitor, the other terminal of said first capacitor being connected to a ground; said connection between said first and second resistors being further connected to said VCO to provide said control signal, and said second filter means comprises a third resistor and said second capacitor, each having two terminals, said resistor being connected at one terminal to said input terminal and at the other terminal to one terminal of said second capacitor, the other terminal of said second capacitor being connected to said ground; and wherein further said interconnection means comprises a pair of oppositely-poled diodes, connected in parallel between said connection between said second resistor and said first capacitor, and said connection between said third resistor and said second capacitor.