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US3993957A
Expired / Lapsed
US
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Clock converter circuit
Assignee: International Business Machines Corp
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Filing: 1976-03-08
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Granted: 1976-11-23
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Expires: 1996-03-08
Abstract
Abstract This invention discloses a structure whereby a fixed frequency machine clocking signal can be multiplied in frequency by any desired integral value. The device uses a tapped delay line having a total time delay slightly less than the time of one-half cycle of the clocking signal and an exclusive-OR tree connected to the taps of the delay line to generate a higher frequency output clock signal. By interposing a known frequency division network to the input of the delay line, the output clock signal can be generated with any desired rational relationship to the driving clocking signal.
Inventors
- 👤 David William Davenport
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:07
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
126 words
A frequency multiplying device for generating an output signal which is an integral harmonic of a square wave input signal, said device comprising: a signal delay line having input and output terminals and at least one tap, the time delay from any terminal or tap to an adjacent terminal or tap being equal to 1/2mC where m is a frequency multiplying factor and C is the frequency of said input signal, said delay line having a total time delay of at least m-1/2mC; and a parity tree connected to m consecutive ones of said terminals and taps, said parity tree operating to supply a significant output signal when any one of a group of selected combinations of input signals is present at said terminals and taps.
Claim 2
Dependent Claim
126 words
A frequency multiplying device for generating an output signal which is an integral harmonic of a square wave input signal, said device comprising: a signal delay line having input and output terminals and at least one tap, the time delay from any terminal or tap to an adjacent terminal or tap being equal to 1/2mC where m is a frequency multiplying factor and C is the frequency of said input signal, said delay line having a total time delay of at least m-1/2mC; and a parity tree connected to m consecutive ones of said terminals and taps, said parity tree operating to supply a significant output signal when any one of a group of selected combinations of input signals is present at said terminals and taps.
Claim 3
Dependent Claim
59 words
A frequency multiplying device as set out in claim 1, including: a frequency divider in the input circuit of said delay line, said divider acting to generate a square wave output having a frequency of 1/n times an input clock signal; and a connection to conduct the output of said frequency divider to said input of said delay line.
Claim 4
Dependent Claim
116 words
A frequency multiplying device to generate a square wave output having a frequency of m times a square wave input signal, said device comprising: a delay line having an input terminal to receive said input signal and a plurality of delay sections connected in series and to said input, each delay section having a time delay of 1/2m of the frequency of said input signal; and a logic section having m inputs, each input connected to a different one of said input and the connections between delay line sections, and a plurality of logic circuits connected to said inputs and operative to generate a square wave output having a frequency of m times said input signal.
Claim 5
Dependent Claim
116 words
A frequency multiplying device to generate a square wave output having a frequency of m times a square wave input signal, said device comprising: a delay line having an input terminal to receive said input signal and a plurality of delay sections connected in series and to said input, each delay section having a time delay of 1/2m of the frequency of said input signal; and a logic section having m inputs, each input connected to a different one of said input and the connections between delay line sections, and a plurality of logic circuits connected to said inputs and operative to generate a square wave output having a frequency of m times said input signal.
Claim 6
Dependent Claim
62 words
A frequency multiplying device as set out in claim 3, and including therewith: a frequency dividing circuit in series with said multiplying circuit and operating to provide at its output a square wave type signal having a frequency of 1/n times its incoming signal whereby said multiplying-dividing circuit will generate an output signal having a relationship of m/n times said input signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-11-23 | 1980-05-24 | 1980-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-11-23 | 1984-05-24 | 1984-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-11-23 | 1988-05-24 | 1988-11-23 | $7700.00 | Window Closed / Lapsed |