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US3991301A Expired / Lapsed US ⏱️ 0.0 years remaining

Logarithmic frequency to voltage converter

Assignee: Westinghouse Electric Corp
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Filing: 1975-05-29
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Granted: 1976-11-09
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Expires: 1995-05-29
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Abstract

Abstract A clock driven digital pattern generator responds to input pulses by generating a digital pattern output corresponding to a predetermined geometric sequence, and a digital to analog converter converts the digital pattern into an analog output signal which is a logarithmic function of the frequency of the input pulses.

Inventors

  • 👤 Anthony G. Chaprnka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 05:17
CPC Classifications
G; G06; G06J; G06J1/00; G01; G01R; G01R23/00; G01R23/02; G01R23/06; H; H03; H03M; H03M1/00; H03M1/66; H03M1/664; H03M1/86

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 154 words
A frequency to voltage converter for developing an analog output signal which is a logarithmic function of the frequency of input pulses, comprising, clock means for producing clock pulses at a constant pulse rate, a digital pattern generator having an input connected to said clock means and a plurality of outputs, said digital pattern generator responding to input pulses occurring at a frequency less than said clock pulses by converting the clock pulses received between successive input pulses into a digital pattern at said outputs which is representative of a predetermined geometric sequence, input pulse generating means connected to said digital pattern generator for producing said input pulses, and digital to analog converter means connected to said outputs of said digital pattern generator and responding to successive digital patterns developed in response to said input pulses by producing an analog output signal which is a logarithmic function of the frequency of said input pulses.
Claim 2
Dependent Claim 154 words
A frequency to voltage converter for developing an analog output signal which is a logarithmic function of the frequency of input pulses, comprising, clock means for producing clock pulses at a constant pulse rate, a digital pattern generator having an input connected to said clock means and a plurality of outputs, said digital pattern generator responding to input pulses occurring at a frequency less than said clock pulses by converting the clock pulses received between successive input pulses into a digital pattern at said outputs which is representative of a predetermined geometric sequence, input pulse generating means connected to said digital pattern generator for producing said input pulses, and digital to analog converter means connected to said outputs of said digital pattern generator and responding to successive digital patterns developed in response to said input pulses by producing an analog output signal which is a logarithmic function of the frequency of said input pulses.
Claim 3
Dependent Claim 225 words
A frequency to voltage converter for developing an analog output signal which is a logarithmic function of the frequency of input pulses, comprising, clock means for producing clock pulses at a constant pulse rate, a digital pattern generator having an input connected to said clock means and a plurality of outputs, said digital pattern generator responding to input pulses occurring at a frequency less than said clock pulses by converting the clock pulses received between successive input pulses into a digital pattern at said outputs which is representative of a predetermined geometric sequence, and input pulse generating means connected to said digital pattern generator for producing said input pulses, said digital pattern generator including a multi-stage ripple counter means having said clock pulses as a first input and said input pulses as a second input, said multi-stage ripple counter means having a plurality of outputs and producing a geometric sequence of signals at said outputs in response to clock pulses received between input pulses, and a latching circuit means connected to each output of said multi-stage ripple counter means, each latching circuit means producing a change in output voltage from a first level to a second level in response to an output signal from the corresponding output of said multi-stage counter means, the output voltage levels of said latching circuit means producing said digital pattern.
Claim 4
Dependent Claim 225 words
A frequency to voltage converter for developing an analog output signal which is a logarithmic function of the frequency of input pulses, comprising, clock means for producing clock pulses at a constant pulse rate, a digital pattern generator having an input connected to said clock means and a plurality of outputs, said digital pattern generator responding to input pulses occurring at a frequency less than said clock pulses by converting the clock pulses received between successive input pulses into a digital pattern at said outputs which is representative of a predetermined geometric sequence, and input pulse generating means connected to said digital pattern generator for producing said input pulses, said digital pattern generator including a multi-stage ripple counter means having said clock pulses as a first input and said input pulses as a second input, said multi-stage ripple counter means having a plurality of outputs and producing a geometric sequence of signals at said outputs in response to clock pulses received between input pulses, and a latching circuit means connected to each output of said multi-stage ripple counter means, each latching circuit means producing a change in output voltage from a first level to a second level in response to an output signal from the corresponding output of said multi-stage counter means, the output voltage levels of said latching circuit means producing said digital pattern.
Claim 5
Dependent Claim 28 words
A frequency to voltage converter as claimed in claim 2 wherein said digital to analog converter includes a summing resistor network operatively connected to said latching circuit means.
Claim 6
Dependent Claim 24 words
A frequency to voltage converter means as claimed in claim 2 wherein said multi-stage ripple counter means is an n bit binary ripple counter.
Claim 7
Dependent Claim 64 words
A frequency to voltage converter means as claimed in claim 2 wherein said analog voltage signal is represented as: V.sub.out = k log (f.sub.in /f.sub.ref), where V out is the analog output signal, f in is the frequency of the input pulses, and f ref is the frequency of the clock pulses divided by the number of stages in the multi-stage ripple counter means.
Claim 8
Dependent Claim 28 words
A frequency to voltage converter as claimed in claim 2 wherein said input pulse functions to reset both said multi-stage ripple counter means and said latching circuit means.
Claim 9
Dependent Claim 57 words
A frequency to voltage converter claimed in claim 2 further including a digital to analog converter means connected to the outputs of said latching circuit means and responding to successive digital patterns developed in response to said input pulses by producing an analog output signal which is a logarithmic function of the frequency of said input pulses.
Claim 10
Dependent Claim 373 words
A frequency to voltage converter for developing an analog output signal which is a logarithmic function of the frequency of input pulses, comprising, clock means for producing clock pulses at a constant pulse rate, a digital pattern generator having an input connected to said clock means and a plurality of outputs, said digital pattern generator responding to input pulses occurring at a frequency less than said clock pulses by converting the clock pulses received between successive input pulses into a digital pattern at said outputs which is representative of a predetermined geometric sequence, an converter for developing an analog output signal which is a logarithmic function of the frequency of input pulses, comprising, clock means for producing clock pulses at a constant pulse rate, a digital pattern generator having an input connected to said clock means and a plurality of outputs, said digital pattern generator responding to input pulses occurring at a frequency less than said clock pulses by converting the clock pulses received between successive input pulses into a digital pattern at said outputs which is representative of a predetermined geometric sequence, and input pulse generating means connected to said digital pattern generator for producing said input pulses, said digital pattern generator including a multi-stage ripple counter means having said clock pulses as a first input and said input pulses as a second input, said multi-stage ripple counter means having a plurality of outputs and producing a geometric sequence of signals at said outputs in response to clock pulses received between input pulses, and a latching circuit means connected to each output of said multi-stage ripple counter means, each latching circuit means producing a change in output voltage from a first level to a second level in response to an output signal from the corresponding output of said multi-stage counter means, the output voltage input pulses generating means connected to said digital pattern generator for producing said input pulses, said digital pattern generator including a multi-stage ripple counter means having clock pulses as a first input and input pulses as a second input, said multi-stage ripple counter means having a plurality of outputs and producing a geometric sequence of signals at said outputs in response to clock pulses received between input pulses.
Claim 11
Dependent Claim 373 words
A frequency to voltage converter for developing an analog output signal which is a logarithmic function of the frequency of input pulses, comprising, clock means for producing clock pulses at a constant pulse rate, a digital pattern generator having an input connected to said clock means and a plurality of outputs, said digital pattern generator responding to input pulses occurring at a frequency less than said clock pulses by converting the clock pulses received between successive input pulses into a digital pattern at said outputs which is representative of a predetermined geometric sequence, an converter for developing an analog output signal which is a logarithmic function of the frequency of input pulses, comprising, clock means for producing clock pulses at a constant pulse rate, a digital pattern generator having an input connected to said clock means and a plurality of outputs, said digital pattern generator responding to input pulses occurring at a frequency less than said clock pulses by converting the clock pulses received between successive input pulses into a digital pattern at said outputs which is representative of a predetermined geometric sequence, and input pulse generating means connected to said digital pattern generator for producing said input pulses, said digital pattern generator including a multi-stage ripple counter means having said clock pulses as a first input and said input pulses as a second input, said multi-stage ripple counter means having a plurality of outputs and producing a geometric sequence of signals at said outputs in response to clock pulses received between input pulses, and a latching circuit means connected to each output of said multi-stage ripple counter means, each latching circuit means producing a change in output voltage from a first level to a second level in response to an output signal from the corresponding output of said multi-stage counter means, the output voltage input pulses generating means connected to said digital pattern generator for producing said input pulses, said digital pattern generator including a multi-stage ripple counter means having clock pulses as a first input and input pulses as a second input, said multi-stage ripple counter means having a plurality of outputs and producing a geometric sequence of signals at said outputs in response to clock pulses received between input pulses.

References Cited (Backward Citations)

US3426184A Cited
US3579127A Cited
US3698631A Cited
US3878383A Cited
US3866024A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-11-09 1980-05-10 1980-11-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-11-09 1984-05-10 1984-11-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-11-09 1988-05-10 1988-11-09 $7700.00 Window Closed / Lapsed

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