Apparatus for generating a logarithmically related series of digitally coded signal quantities

Claim 2

Apparatus for generating a logarithmically related series of digitally coded signal quantities comprising: an accumulator for storing a digitally coded numerical quantity; an adder for producing output signals representative of the sum of two digitally coded signal quantities applied thereto; means for applying said stored digitally coded signal quantity to said adder; means for applying a predetermined constant fraction of said stored digitally coded signal quantity to said adder; and means for applying said output signals of said adder to said accumulator.

Claim 5

Apparatus for generating a logarithmically related series of digitally coded signal quantities comprising: means for generating a series of control pulses; a storage register for storing an applied digitally coded signal quantity in response to each of said control pulses and for producing a digitally coded output signal representative of said stored signal quantity; an adder for producing a digitally coded output signal representative of the sum of two digitally coded signal quantities applied thereto; first means for applying said stored digitally coded signal quantity to said adder; second means for applying said stored digitally coded signal quantity to said aDder with numerical significance reduced relative to the numerical significance of said digitally coded signal quantity as applied to said adder by said first means; and means for supplying said adder output signal to said storage register.

Claim 6

Apparatus for generating a logarithmically related series of digitally coded signal quantities comprising: means for generating a series of control pulses; a storage register for storing an applied digitally coded signal quantity in response to each of said control pulses and for producing a digitally coded output signal representative of said stored signal quantity; an adder for producing a digitally coded output signal representative of the sum of two digitally coded signal quantities applied thereto; first means for applying said stored digitally coded signal quantity to said adder; second means for applying said stored digitally coded signal quantity to said aDder with numerical significance reduced relative to the numerical significance of said digitally coded signal quantity as applied to said adder by said first means; and means for supplying said adder output signal to said storage register.

Claim 7

The apparatus of claim 3 wherein said means for generating a series of control pulses further comprises: first source of timing pulses; and means for periodically enabling said first source of timing pulses.

Claim 8

The apparatus of claim 4 wherein said first source of timing pulses further comprises: a signal generator for generating said timing pulses; means for counting said timing pulses; a comparator for producing an output signal indicative of whether or not the count of said timing pulses is less than or equal to a predetermined reference quantity; and means responsive to said comparator output signal for applying said timing pulses to said storage register as said series of control pulses when said count of said timing pulses is less than or equal to said reference quantity.

Claim 9

The apparatus of claim 5 wherein said means for periodically enabling said first source of timing signals further comprises: a second source of timing pulses, said timing pulses produced by said second source having a frequency substantially lower than the frequency of said timing pulses produced by said first source; and means responsive to each of said timing pulses produced by said second source of timing pulses for resetting said means for counting.

Claim 10

The apparatus of claim 3 wherein said means for generating a series of control pulses further comprises: a source of relatively high frequency pulses; means for counting said high frequency pulses; means for comparing the count of said high frequency pulses to a predetermined reference quantity; means for applying said high frequency pulses to said storage register as said series of control pulses when said count of said high frequency pulses bears a predetermined relationship to said reference quantity; a source of relatively low frequency pulses; and means responsive to each of said low frequency pulses for resetting said counting means.

Claim 11

The apparatus of claim 3 wherein said means for generating a series of control pulses further comprises: a source of relatively high frequency timing pulses; means for counting said high frequency timing pulses; comparator means for producing an output signal indicative of whether or not the count of said high frequency timing pulses is less than or equal to a predetermined reference quantity; means responsive to said output signal of said comparator means for applying said high frequency pulses to said storage register as said series of control pulses when said count of said high frequency pulses is less than or equal to said reference quantity; a source of relatively low frequency pulses; and means responsive to each of said low frequency pulses for resetting said counting means.

Claim 12

Apparatus for generating a logarithmically related series of digitally coded signal quantities comprising: a first source of timing pulses; means for periodically enabling said first source of timing pulses; an accumulator for storing a digitally coded numerical quantity; an adder for producing output signals representative of the sum of two digitally coded signal quantities applied thereto; first means for applying said stored digitally coded signal quantity to said adder; second means for applying said stored digitally coded signal quantity to said adder with numerical significance reduced relative to the numerical significance of said digitally coded signal quantity as applied to said adder by said first means; and means for applying said output signals of said adder to said accumulator, said accumulator being arranged to store said sum represented by said adder output signals in response to a pulse from said first source of timing pulseS.

Claim 13

Apparatus for generating a logarithmically related series of digitally coded signal quantities comprising: a first source of timing pulses; means for periodically enabling said first source of timing pulses; an accumulator for storing a digitally coded numerical quantity; an adder for producing output signals representative of the sum of two digitally coded signal quantities applied thereto; first means for applying said stored digitally coded signal quantity to said adder; second means for applying said stored digitally coded signal quantity to said adder with numerical significance reduced relative to the numerical significance of said digitally coded signal quantity as applied to said adder by said first means; and means for applying said output signals of said adder to said accumulator, said accumulator being arranged to store said sum represented by said adder output signals in response to a pulse from said first source of timing pulseS.

Claim 14

The apparatus of claim 9 wherein said first source of timing pulses further comprises: a signal generator for generating said timing pulses; means for counting said timing pulses; a comparator for producing an output signal indicative of whether or not the count of said timing pulses is less than or equal to a predetermined reference quantity; and means responsive to said comparator output signal for applying said timing pulses to said accumulator when said count of said timing pulses is less than or equal to said reference quantity.

Claim 15

The apparatus defined in claim 10 wherein said means for periodically enabling said first source of timing pulses further comprises: a second source of timing pulses having frequency substantially lower than the frequency of the timing pulses produced by said first source of timing pulses; and means responsive to each of said timing pulses produced by said second source of timing pulses for resetting said means for counting.

Claim 16

Apparatus for generating a logarithmically related series of digitally coded signal quantities comprising: a source of relatively low frequency timing pulses; a source of relatively high frequency timing pulses responsive to said source of relatively low frequency timing pulses for producing a predetermined number of high frequency timing pulses in response to each of said low frequency timing pulses; an accumulator for storing an applied digitally coded signal quantity in response to each of said high frequency timing pulses and for producing a digitally coded output signal representative of said stored quantity; an adder for producing a digitally coded output signal representative of the sum of two applied digitally coded signal quantities; means for applying said accumulator output signal to said adder; means responsive to said accumulator output signal for producing a digitally coded output signal representative of said stored quantity reduced in significance by a predetermined numerical factor and for applying said digitally coded output signal to said adder; and means for applying said adder output signal to said accumulator.

Claim 17

Apparatus for generating a logarithmically related series of digitally coded signal quantities comprising: a source of relatively low frequency timing pulses; a source of relatively high frequency timing pulses responsive to said source of relatively low frequency timing pulses for producing a predetermined number of high frequency timing pulses in response to each of said low frequency timing pulses; an accumulator for storing an applied digitally coded signal quantity in response to each of said high frequency timing pulses and for producing a digitally coded output signal representative of said stored quantity; an adder for producing a digitally coded output signal representative of the sum of two applied digitally coded signal quantities; means for applying said accumulator output signal to said adder; means responsive to said accumulator output signal for producing a digitally coded output signal representative of said stored quantity reduced in significance by a predetermined numerical factor and for applying said digitally coded output signal to said adder; and means for applying said adder output signal to said accumulator.

Claim 18

The apparatus of claim 12 wherein said source of high frequency timing pulses further comprises: a signal generator for generating said high frequency timing pulses; a counter responsive to said signal generator for producing an output signal indicative of the number of said high frequency timing pulses that have been generated, said counter being reset by each of said low frequency timing pulses; a comparator responsive to said counter output signal for producing an output signal indicative of whether or not said number of said high frequency timing pulses is less than or equal to a predetermined reference quantity; and means responsive to said comparator output signal for applying said high frequency timing pulses to said accumulator when said number of said high frequency timing pulses is less than or equal to said predetermined reference quantity.

Claim 19

Apparatus for generating a logarithmically related series of digitally coded signal quantities, said series starting with a predetermined initial quantity and ending when said generated signal quantities exceed a predetermined final quantity, comprising: an accumulator for storing an applied digitally coded numerical quantity; means for applying said predetermined initial quantity to said accumulator at the start of the operation of said apparatus; a source of timing pulses; means for periodically enabling said source of timing pulses; an adder for producing output signals representative of said sum of two digitally coded signal quantities applied thereto; first means for applying said stored digitally coded signal quantity to said adder; second means for applying said stored digitally coded signal quantity to said adder with numerical significance reduced relative to the numerical significance Of said digitally coded signal quantity as applied to said adder by said first means; means for applying said output signals of said adder to said accumulator, said accumulator being arranged to store said sum represented by said adder output signals in response to a pulse from said source of timing pulses; means for applying said timing pulses to said accumulator; and means responsive to said stored digitally coded signal quantity for disabling said means for periodically enabling when said stored quantity exceeds said predetermined final quantity.

Claim 20

Apparatus for generating a logarithmically related series of digitally coded signal quantities, said series starting with a predetermined initial quantity and ending when said generated signal quantities exceed a predetermined final quantity, comprising: an accumulator for storing an applied digitally coded numerical quantity; means for applying said predetermined initial quantity to said accumulator at the start of the operation of said apparatus; a source of timing pulses; means for periodically enabling said source of timing pulses; an adder for producing output signals representative of said sum of two digitally coded signal quantities applied thereto; first means for applying said stored digitally coded signal quantity to said adder; second means for applying said stored digitally coded signal quantity to said adder with numerical significance reduced relative to the numerical significance Of said digitally coded signal quantity as applied to said adder by said first means; means for applying said output signals of said adder to said accumulator, said accumulator being arranged to store said sum represented by said adder output signals in response to a pulse from said source of timing pulses; means for applying said timing pulses to said accumulator; and means responsive to said stored digitally coded signal quantity for disabling said means for periodically enabling when said stored quantity exceeds said predetermined final quantity.