Absolute-value circuit

Claim 2

A circuit for translating an alternating input signal current to a load current comprising, in combination: first and second complementary current mirror amplifiers, each having an input current path and first and second output current paths through each of which flows a current proportionally related to its respective input current, said first current mirror amplifier connected to its output current paths to the corresponding paths of said second current mirror amplifier; means for applying a quiescent current to the input current paths of each of said current mirror amplifiers; means for applying said input signal current to said input current path of said second current mirror amplifier for thereby conditioning both output paths of said second current mirror amplifier to accept an amount of current proportional to the total current flowing through the input current path of said second current mirror amplifier; a third current path connected in shunt with said second current path of said second current mirror amplifier; means coupled to the first output current path of said second current mirror amplifier and to said third current path, responsive to the conditioning of said first output current path of the second current mirror amplifier to accept more current than the first output current path of the first current mirror amplifier can provide for cutting off said third current path, and responsive to the conditioning of the first output current path of the second current mirror amplifier to accept less current than the first output current path of the first current mirror provides for closing the third current path; and a load circuit connected to the second current path of the second current mirror amplifier and to said third current path for supplying a flow of current to the one of these paths demanding more current than the second current path of the first current mirror amplifier can provide.

Claim 3

The combination recited in claim 1 wherein the input current path of said first current mirror amplifier is connected to and supplies its quiescent current to the input current path of said second current mirror amplifier.

Claim 4

The combination of claim 1 further including a third current mirror amplifier having an input and an output current path, said third current path comprising the output current path of said third current mirror amplifier and said means responsive to the conditioning of said first output current path comprising said input current path of said third current mirror amplifier.

Claim 5

The combination recited in claim 1 where said first current mirror amplifier further includes a third output current path coupled to the input current path of said second current mirror amplifier and supplying its output current as the quiescent input current to said second current mirror amplifier.

Claim 6

The combination recited in claim 1, further including a circuit common terminal, and wherein said second current mirror amplifier first output current path comprises the collector-emitter path of a transistor, the emitter of said transistor connected to said circuit common terminal, said transistor further including a base region, further including means for quiescently maintaining said base region at a first potential with respect to said circuit common terminal.

Claim 7

The combination recited in claim 5, further including means for preventing said first potential from exceeding the potential at the collector of said transistor.

Claim 8

The combination recited in claim 6 wherein said means for preventing comprises a second transistor of the same conductivity type as the first-mentioned transistor and having base, collector and emitter regions, the collector-emitter path of said second transistor serially-connected between said second current mirror amplifier first output current path and said first-mentioned transistor collector-emitter path and poled in the same direction as said first-mentioned transistor, the emitter of said second transistor connected to the collector of said first-mentioned transistor and further including means for maintaining said second transistor base at a second potential, said second potential in excess of said first potential.

Claim 9

The combination recited in claim 7 further including a third current mirror amplifier having an input current path coupled between said circuit common terminal and the collector electrode of said second transistor, said means responsive to the conditioning of said first output current path comprising said input current path, said third current mirror also having an output current path comprising said third current path.

Claim 10

The combination recited in claim 8 further including a diode serving as the connection between said third current mirror amplifier input current path and said circuit common terminal.

Claim 11

The combination as set forth in claim 1 wherein said input current path of said second current mirror amplifier comprises a first diode, wherein the first output current path of said second current mirror amplifier comprises the emitter-to-collector path of a transistor, said transistor also having a base-emitter junction, said first diode being connected in the forward direction, across said junction, further including a second diode connected at one of its electrodes to the electrode of the first diode at the emitter electrode of said transistor, like-electrode-to-like-electrode, and a signal source connected between the other electrodes of said first and second diodes.

Claim 12

A circuit for translating a signal current comprising, in combination: a constant current source; a first current path receptive of the current supplied by said source; a second current path receptive of the current supplied by said source; load means; a second current source, connected to supply current to said first and second current paths, through said load means; and means responsive to the signal current when of one sense for opening said second current path and conditioning said first current path to accept more current than said constant current source provides, whereby the remainder of said current flows from said second current source through said load means to said first current path, and responsive to the signal current when of opposite sense for conditioning said first current path to accept less current than said constant current source provides, and for closing said second current path and conditioning it to accept more than the difference between the amount of current provided by said constant current source and that accepted by said first current path, whereby the remainder of said current flows from said second current source through said load means to said second current path.

Claim 13

A circuit for translating a signal current comprising, in combination: a constant current source; a first current path receptive of the current supplied by said source; a second current path receptive of the current supplied by said source; load means; a second current source, connected to supply current to said first and second current paths, through said load means; and means responsive to the signal current when of one sense for opening said second current path and conditioning said first current path to accept more current than said constant current source provides, whereby the remainder of said current flows from said second current source through said load means to said first current path, and responsive to the signal current when of opposite sense for conditioning said first current path to accept less current than said constant current source provides, and for closing said second current path and conditioning it to accept more than the difference between the amount of current provided by said constant current source and that accepted by said first current path, whereby the remainder of said current flows from said second current source through said load means to said second current path.

Claim 14

A circuit as set forth in claim 11, further including a first current mirror amplifier, said second current path comprising the output circuit of said current mirror amplifier, said output circuit being connected in shunt with said first path, and said means responsive to the signal current comprising the input circuit to said current mirror amplifier.

Claim 15

A circuit for translating an input signal current to a load current comprising, in combination: a first current mirror amplifier comprising a first common terminal, a first input terminal and first and second output terminals, two transistors of the same conductivity type, each having base, emitter and collector electrodes, connected at their emitter electrodes to said common terminal, at their base electrodes to said input terminal, and at their respective collector electrodes to said first and second output terminals, respectively, and first diode means connected between said common and input terminals, in the same polarity as the base-emitter paths of said transistors; a second current mirror amplifier comprising a second common terminal, a second input terminal, and first and second output terminals connected to said first and second output terminals, respectively, of said first current mirror amplifier, said second current mirror amplifier including two transistors of opposite conductivity type to the transistors of said first current mirror amplifier, each having base, emitter and collector electrodes, each connected at its emitter electrode to said second common terminal and at its base electrode to said second input terminal, and the respective collector electrodes of said transistors of said second current mirror amplifier being connected to said first and second output terminals of said second current mirror amplifier, respectively, said second current mirror amplifier including also diode means connected between said second common terminal and said second input terminal, and poled in the same direction as the base-to-emitter paths of said transistors of said second current mirror amplifier; means for applying a quiescent current between the input and common terminals of each of said current mirror amplifiers; means for applying said input signal current to said second input terminal, thereby conditioning said second current mirror amplifier to produce a flow of output current at its first and second output terminals proportional to the total current flowing through said second input terminal; a third current mirror amplifier having a third input terminal coupled to the first output terminal of said first current mirror amplifier, a third common terminal coupled to said second common terminal, and an output terminal coupled to the second output terminal of said first current mirror amplifier, said third current mirror amplifier including a transistor of the same conductivity type as the transistors of said second current mirror amplifier having base, emitter and collector electrodes, connected at its base electrode to said third imput terminal, at its emitter electrode to said third common terminal, and at its collector electrode to the output terminal of said third current mirror amplifier, and having also diode means connected between said third input terminal and said third common terminal, and poled in the same direction as the base-emitter path of the transistor of said third current mirror amplifier; a terminal for a reference voltage; and load means connected between said terminal for said reference voltage and said second output terminal of said second current mirror amplifier.

Claim 16

A circuit for translating an input signal current to a load current comprising, in combination: a first current mirror amplifier comprising a first common terminal, a first input terminal and first and second output terminals, two transistors of the same conductivity type, each having base, emitter and collector electrodes, connected at their emitter electrodes to said common terminal, at their base electrodes to said input terminal, and at their respective collector electrodes to said first and second output terminals, respectively, and first diode means connected between said common and input terminals, in the same polarity as the base-emitter paths of said transistors; a second current mirror amplifier comprising a second common terminal, a second input terminal, and first and second output terminals connected to said first and second output terminals, respectively, of said first current mirror amplifier, said second current mirror amplifier including two transistors of opposite conductivity type to the transistors of said first current mirror amplifier, each having base, emitter and collector electrodes, each connected at its emitter electrode to said second common terminal and at its base electrode to said second input terminal, and the respective collector electrodes of said transistors of said second current mirror amplifier being connected to said first and second output terminals of said second current mirror amplifier, respectively, said second current mirror amplifier including also diode means connected between said second common terminal and said second input terminal, and poled in the same direction as the base-to-emitter paths of said transistors of said second current mirror amplifier; means for applying a quiescent current between the input and common terminals of each of said current mirror amplifiers; means for applying said input signal current to said second input terminal, thereby conditioning said second current mirror amplifier to produce a flow of output current at its first and second output terminals proportional to the total current flowing through said second input terminal; a third current mirror amplifier having a third input terminal coupled to the first output terminal of said first current mirror amplifier, a third common terminal coupled to said second common terminal, and an output terminal coupled to the second output terminal of said first current mirror amplifier, said third current mirror amplifier including a transistor of the same conductivity type as the transistors of said second current mirror amplifier having base, emitter and collector electrodes, connected at its base electrode to said third imput terminal, at its emitter electrode to said third common terminal, and at its collector electrode to the output terminal of said third current mirror amplifier, and having also diode means connected between said third input terminal and said third common terminal, and poled in the same direction as the base-emitter path of the transistor of said third current mirror amplifier; a terminal for a reference voltage; and load means connected between said terminal for said reference voltage and said second output terminal of said second current mirror amplifier.

Claim 17

A circuit as set forth in claim 13, further including resistive means connecting said first and second input terminals, and wherein said means applying a quiescent current comprises a voltage source connected between said first and second common terminals.

Claim 18

A circuit as set forth in claim 14 further including in said first current mirror amplifier, a third output terminal connected to said second input terminal, a third transistor of the same conductivity type as the other transistors of said first current mirror amplifier, having base, emitter and collector electrodes, connected at its emitter electrode to said first common terminal, at its collector electrode to said third output terminal and at its base electrode to said first input terminal, said third transistor comprising said means for supplying quiescent current to the second current mirror amplifier, and further including a circuit including resistive means connecting said first input terminal to said second common terminal for providing a path for the quiescent current of said first current mirror amplifier.

Claim 19

A circuit as set forth in claim 13, further including: means coupled to said first output terminal of said second current mirror amplifier for maintaining that terminal at a potential 1V BE above that at said second common terminal; and means responsive to conduction between said third input terminal and said second common terminal for maintaining said third common terminal at a potential 1V BE above that of said second common terminal, where 1V BE is the forward offset voltage across a conducting semiconductor junction.