Patent US3989894A successfully refreshed from Google Patents.
US3989894A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronism error detecting and correcting system for a circulating memory
Assignee: International Standard Electric Corp
•
Filing: 1973-12-13
•
Granted: 1976-11-02
•
Expires: 1993-12-13
Abstract
Abstract A system is disclosed for checking and correcting the synchronism of bits stored in a circulating memory which is part of a PCM switching system. Periodically, bits previously written in an addressable memory are read-out and compared to corresponding bits supplied by the circulating memory. In accordance with results of the comparison, a synchronism signal or a fast or slow correction signal is supplied.
Inventors
- 👤 Pierre Charransol
- 👤 Jacques Salle
- 👤 Jacques Becker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:27
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1666; G06F11/167; G11; G11C; G11C29/00; G11C29/70; G11C29/88; H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/06
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
160 words
A synchronization correction system for a recirculating memory controlled by an address counter, comprising means for feeding a series of address control bits derived from said counter to said memory, an auxiliary memory, enabling means connected to receive said bits and responsive to said bits for feeding one of said bits for storage in said auxiliary memory at a time having predetermined timed relationship to the feeding of bits to said recirculating memory, means for reading out said one bit from said auxiliary memory at a predetermined time interval thereafter, comparison means for comparing the bit read out of said auxiliary memory with bits fed from said enabling means, correction control means responsive to the comparison of said bits for emitting a first signal when the compared bits are identical and emitting second signals when the compared bits are not identical, and means responsive to said second signals for correcting the timing of feeding of bits to said recirculating memory.
Claim 2
Dependent Claim
160 words
A synchronization correction system for a recirculating memory controlled by an address counter, comprising means for feeding a series of address control bits derived from said counter to said memory, an auxiliary memory, enabling means connected to receive said bits and responsive to said bits for feeding one of said bits for storage in said auxiliary memory at a time having predetermined timed relationship to the feeding of bits to said recirculating memory, means for reading out said one bit from said auxiliary memory at a predetermined time interval thereafter, comparison means for comparing the bit read out of said auxiliary memory with bits fed from said enabling means, correction control means responsive to the comparison of said bits for emitting a first signal when the compared bits are identical and emitting second signals when the compared bits are not identical, and means responsive to said second signals for correcting the timing of feeding of bits to said recirculating memory.
Claim 3
Dependent Claim
54 words
A system as claimed in claim 1, wherein said enabling means comprises a plurality of bistable circuits each enabled responsive to successive bits fed to said recirculating memory, and one of said bistable circuits being responsive to said one bit, and others of said bistable circuits responsive to other successive bits of said series.
Claim 4
Dependent Claim
53 words
A system as claimed in claim 2 in which said comparison means comprises a plurality of gates, each gate having as one input thereto an output from one of said enabling means and each said gate having as another input thereto a path for the read out of bits from said auxiliary memory.
References Cited (Backward Citations)
US3368203A
Cited
US3473150A
Cited
US3562710A
Cited
US3560924A
Cited
US3733585A
Cited
US3732547A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-11-02 | 1980-05-03 | 1980-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-11-02 | 1984-05-03 | 1984-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-11-02 | 1988-05-03 | 1988-11-02 | $7700.00 | Window Closed / Lapsed |