Deep diode silicon controlled rectifier

Claim 1

A semiconductor device comprising a body of semiconductor material having a predetermined first type conductivity, a predetermined level of resistivity, two major opposed surfaces comprising the top and bottom surfaces thereof and a lamellar structure of at least four planar regions of alternate and opposite type conductivity formed in situ in the body and extending between, and terminating in, the opposed major surfaces; the body having an axis substantially perpendicular to the two major opposed surfaces and substantially parallel with a first preferred crystal axis of the material of the of the body; at least one of the major opposed surfaces having a preferred crystal planar orientation which is one selected from the group consisting of (111), (110) and (100); a plurality of first planar regions of first regions of first type conductivity comprising at least two of the planar regions; a plurality of second regions of second type conductivity comprising at least two of the planar regions; each of the first and second regions being aligned substantially with a preferred second crystal axis of the body; the material of at least each second region consisting of recrystallized semiconductor material of the body which is formed in situ by the migration of a melt of a metal-rich semiconductor material of the body, which comprises at least one dopant material, by thermal gradient zone melting at a predetermined elevated temperature along a thermal gradient substantially parallel with the first preferred crystal axis and the axis of the body substantially perpendicular to the major surface having the preferred crystal planar orientation, and having a predetermined level of concentration of the metal of the melt as determined by the solid solubility limit of that metal in that semiconductor material at that predetermined elevated temperature of migration and the metal is distributed substantially uniformly throughout the entire region to provide a substantially uniform level of resistivity throughout the entire region and to impart the predetermined type conductivity thereto and having a substantially uniform cross-section throughout the entire region; each of the first and second regions having opposed major surfaces; one of the major surfaces of one of the first regions being coextensive with one of the opposed major surfaces of the body; a first P-N junction formed by the contiguous surfaces of the other opposed major surface of the first region and the mutually adjacent major opposed surface of the adjacent second region; one of the major surfaces of one of the second regions being coextensive with the other of the opposed major surfaces of the body; a second P-N junction formed by the contiguous surfaces of the other of the major opposed surfaces of the second region and one of the adjacent major opposed surfaces of the adjacent first region; a plurality of third P-N junctions, each third P-N junction being formed by a remaining pair of contiguous major opposed surfaces of each pair of mutually adjacent first and second regions of opposite type conductivity; a first electrical contact affixed to, and in an electrical conductive relationship with, a selected surface area of the region which has a surface coextensive with one of the two major opposed surfaces of the body; a second electrical contact affixed to, and in an electrical conductive relationship with, a selected surface area of the other region having a surface coextensive with the other of the two major opposed end surfaces of the body, and gating means for biasing at least one of the first, the second and the plurality of third P-N junctions to at least switch the semiconductor device into an "on" condition.