US3988714A — Computer input/output apparatus for providing not…

Claim 1

Independent Claim 459 words

An integrated interface for providing communication between the central processor and peripheral units of a computer system, wherein the transfer of control information or of data information is preceded by the transmittal of control character information from the central processor, comprising: a channel having a bidirectional bus for transferring information therethrough and having lines for transferring signals therethrough in a single direction, one end of said channel being coupled to said central processor and the other end of said channel being coupled to at least one of said peripheral units; and error identification means coupled to said channel for detecting errors in information and for distinguishing such errors as channel errors, which are errors due to transfer of information over said channel, and logical errors, which are errors in information applied to said channel, and for distinguishing whether or not such errors will adversely affect subsequent operations, said error identification means comprising: a first network for generating parity bits for information immediately prior to said information entering the central processor end of said bus; a first detector for sensing information leaving the peripheral unit end of said bus and responsive thereto for generating a first signal representing the detection of a parity error in control information, a second signal representing the detection of a parity error in data information, and a third signal representing the detection of a logical error in information; a second network for generating parity bits for information immediately prior to said information entering the peripheral unit end of said bus; a second detector for sensing information leaving the central processor end of said bus and responsive thereto for generating a fourth signal representing the detection of a parity error in said information; a first circuit responsive to the signals generated by said first detector for initiating a signal exchange on said lines of said channel to represent the occurrence of an error in information received from the peripheral unit end of said bus; a second circuit responsive to said first and second signals for generating a fifth signal representing the occurrence of a parity error in information received from the peripheral unit end of said bus; a third circuit responsive to said fourth signal for generating signals respectively representing, in data information leaving the central processor end of said bus, the occurrence of a parity error in control information and a parity error in data information; and a fourth circuit responsive to said signal exchange and said fifth signal for generating signals respectively representing, in information leaving the peripheral unit end of said bus, i. the occurrence of a parity error in control information, ii. the occurrence of a parity error in data information, and iii. the occurrence of a logical error in control information.

Claim 2

Dependent Claim 459 words

An integrated interface for providing communication between the central processor and peripheral units of a computer system, wherein the transfer of control information or of data information is preceded by the transmittal of control character information from the central processor, comprising: a channel having a bidirectional bus for transferring information therethrough and having lines for transferring signals therethrough in a single direction, one end of said channel being coupled to said central processor and the other end of said channel being coupled to at least one of said peripheral units; and error identification means coupled to said channel for detecting errors in information and for distinguishing such errors as channel errors, which are errors due to transfer of information over said channel, and logical errors, which are errors in information applied to said channel, and for distinguishing whether or not such errors will adversely affect subsequent operations, said error identification means comprising: a first network for generating parity bits for information immediately prior to said information entering the central processor end of said bus; a first detector for sensing information leaving the peripheral unit end of said bus and responsive thereto for generating a first signal representing the detection of a parity error in control information, a second signal representing the detection of a parity error in data information, and a third signal representing the detection of a logical error in information; a second network for generating parity bits for information immediately prior to said information entering the peripheral unit end of said bus; a second detector for sensing information leaving the central processor end of said bus and responsive thereto for generating a fourth signal representing the detection of a parity error in said information; a first circuit responsive to the signals generated by said first detector for initiating a signal exchange on said lines of said channel to represent the occurrence of an error in information received from the peripheral unit end of said bus; a second circuit responsive to said first and second signals for generating a fifth signal representing the occurrence of a parity error in information received from the peripheral unit end of said bus; a third circuit responsive to said fourth signal for generating signals respectively representing, in data information leaving the central processor end of said bus, the occurrence of a parity error in control information and a parity error in data information; and a fourth circuit responsive to said signal exchange and said fifth signal for generating signals respectively representing, in information leaving the peripheral unit end of said bus, i. the occurrence of a parity error in control information, ii. the occurrence of a parity error in data information, and iii. the occurrence of a logical error in control information.

Claim 3

Dependent Claim 140 words

The interface of claim 1, further comprising: a first register for receiving control information leaving the peripheral unit end of said bus; a second register for receiving data information leaving the peripheral unit end of said bus; and wherein said first detector comprises: first sensing means coupled to said first register for detecting a parity error in the contents of said first register and for generating said first signal upon detection of a parity error, second sensing means coupled to said second register for detecting a parity error in the contents of said second register and for generating said second signal upon detection of a parity error, and third sensing means coupled to said second register for detecting a logical error in the contents of said second register and for generating said third signal upon detection of a logical error.

Claim 4

Dependent Claim 286 words

An interface for providing the transfer of control and data characters between a central processor and a peripheral unit, comprising: a channel for transferring characters between first and second ends thereof, said first end being coupled to said central processor and said second end being coupled to said peripheral unit; parity generation circuits for generating parity bits for each of said characters immediately prior to said character entering said channel; parity check circuits for testing each of said characters immediately after said characters emerge from said channel and for generating first signals representing the detection of parity errors in said characters; code check circuits for testing each of said characters immediately after said characters emerge from the second end of said channel and for generating second signals representing the detection of erroneous codes in said characters; first notification means responsive to both said first and second signals for generating third signals for notifying said central processor of the occurrence of an error in characters emerging from the second end of said channel; second notification means responsive to said first signals for generating a fourth signal for notifying said central processor of the occurrence of a parity error in characters emerging from the second end of said channel; and a first circuit responsive to said third and fourth signals for providing immediate notification to the central processor of the occurrence of said third and fourth signals when the error represented by said third and fourth signals has been detected in a control character, but for delaying notification to the central processor of the occurrence of said third and fourth signals when the error represented by said third and fourth signals has been detected in a data character.

Claim 5

Dependent Claim 286 words

An interface for providing the transfer of control and data characters between a central processor and a peripheral unit, comprising: a channel for transferring characters between first and second ends thereof, said first end being coupled to said central processor and said second end being coupled to said peripheral unit; parity generation circuits for generating parity bits for each of said characters immediately prior to said character entering said channel; parity check circuits for testing each of said characters immediately after said characters emerge from said channel and for generating first signals representing the detection of parity errors in said characters; code check circuits for testing each of said characters immediately after said characters emerge from the second end of said channel and for generating second signals representing the detection of erroneous codes in said characters; first notification means responsive to both said first and second signals for generating third signals for notifying said central processor of the occurrence of an error in characters emerging from the second end of said channel; second notification means responsive to said first signals for generating a fourth signal for notifying said central processor of the occurrence of a parity error in characters emerging from the second end of said channel; and a first circuit responsive to said third and fourth signals for providing immediate notification to the central processor of the occurrence of said third and fourth signals when the error represented by said third and fourth signals has been detected in a control character, but for delaying notification to the central processor of the occurrence of said third and fourth signals when the error represented by said third and fourth signals has been detected in a data character.

Claim 6

Dependent Claim 83 words

The interface of claim 3, further comprising: a second circuit responsive to said first signals for generating a fifth signal for notifying said central processor of the occurrence of a parity error in characters emerging from the first end of said channel; and wherein said first circuit is further responsive to said fifth signal for providing immediate or delayed notification according to whether the error represented by said fifth signal has been detected respectively in a control character or in a data character.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1979-10-26	1980-04-26	1980-10-26	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1983-10-26	1984-04-26	1984-10-26	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1987-10-26	1988-04-26	1988-10-26	$7700.00	Window Closed / Lapsed

Computer input/output apparatus for providing notification of and distinguishing among various kinds of errors

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag