Controlled capacitive filter for active loads

Claim 2

A power circuit with a controlled capacitive filter comprising a single phase full wave rectifier having a pair of input terminals connectable to a source of low frequency alternating-current line voltage and positive and negative output terminals at which full wave rectified line voltage is produced, a controlled capacitive filter connected between selected rectifier terminals and including a filter capacitor and a first gate controlled thyristor for controlling charging of said filter capacitor which are connected in series in a circuit coupled between said rectifier output terminals, and further including means comprised by at least a second gate controlled thyristor for controlling discharge of said filter capacitor, an active load circuit supplied with voltage by said controlled filter and producing a regulated unidirectional output voltage, first sensing and gating means for rendering conductive said first gate controlled thyristor at a preselected delay after said filter capacitor has completely discharged, and second sensing and gating means for rendering conductive said second gate controlled thyristor for conduction during the intervals when the instantaneous full wave rectified line voltage is below the regulated unidirectional output voltage.

Claim 3

A power circuit according to claim 1 wherein the circuit coupled between said rectifier output terminals further includes a diode connected between said positive rectifier output terminal and filter capacitor, said second gate controlled thyristor being connected between said positive rectifier output terminal and a junction between said filter capacitor and first gate controlled thyristor.

Claim 4

A power circuit according to claim 1 wherein the circuit coupled between said rectifier output terminals further includes an inductor in series between said filter capacitor and first gate controlled thyristor, and said sensing and gating means for rendering conductive said first gate controlled thyristor effects resonant charging of said filter capacitor by delaying gating until near the peak rectified line voltage.

Claim 5

A power circuit according to claim 1 wherein said second gate controlled thyristor is connected between one rectifier input terminal and a junction between said filter capacitor and first gate controlled thyristor, and said means for controlling discharge of said filter capacitor further includes a third gate controlled thyristor connected between the other rectifier input terminal and the junction between said filter capacitor and first gate controlled thyristor, said second sensing and gating means rendering conductive said second and third gate controlled thyristors depending on the line voltage polarity.

Claim 6

A power circuit according to claim 1 wherein said means for controlling discharge of said filter capacitor further includes a pair of diodes respectively connected in series with said second gate controlled thyristor between said rectifier input terminals and a junction between said filter capacitor and first gate controlled thyristor.

Claim 7

A power circuit according to claim 1 wherein said first sensing and gating means includes current sensor means and a delay circuit actuated by resumption of current flow after said filter capacitor has completely discharged for generating a gating pulse supplied to said first gate controlled thyristor, and said second sensing and gating means includes first voltage sensor means for sensing the instantaneous full wave rectified line voltage and generating a first sensor signal indicative thereof, second voltage sensor means for sensing the instantaneous unidirectional output voltage and generating a second sensor signal indicative thereof, and means for comparing said sensor signals and generating a gating pulse supplied to said second gate controlled thyristor.

Claim 8

A power circuit with a controlled capacitive filter for use with an active load circuit having a predetermined unidirectional output voltage comprising a single phase full wave rectifier having a pair of input terminals connectable to a source of low frequency alternating-current line voltage and producing full wave rectified line voltage at a pair of output terminals, a controlled capacitive filter connected between selected rectifier terminals and including a filter capacitor and first gate controlled thyristor for controlling charging of said filter capacitor which are connected in series in a circuit coupled between said rectifier output terminals, said controlled filter further including means comprised by at least a second gate controlled thyristor for controlling discharge of said filter capacitor and operative to connect said filter capacitor in series between a predetermined positive rectifier terminal and the active load circuit in each half cycle of the line voltage, means for rendering conductive said first gate controlled thyristor at a preselected delay after said filter capacitor has completely discharged, and means for rendering conductive said second gate controlled thyristor for conduction during the intervals when the instantaneous full wave rectified line voltage is below the predetermined unidirectional output voltage.

Claim 9

A power circuit with a controlled capacitive filter for use with an active load circuit having a predetermined unidirectional output voltage comprising a single phase full wave rectifier having a pair of input terminals connectable to a source of low frequency alternating-current line voltage and producing full wave rectified line voltage at a pair of output terminals, a controlled capacitive filter connected between selected rectifier terminals and including a filter capacitor and first gate controlled thyristor for controlling charging of said filter capacitor which are connected in series in a circuit coupled between said rectifier output terminals, said controlled filter further including means comprised by at least a second gate controlled thyristor for controlling discharge of said filter capacitor and operative to connect said filter capacitor in series between a predetermined positive rectifier terminal and the active load circuit in each half cycle of the line voltage, means for rendering conductive said first gate controlled thyristor at a preselected delay after said filter capacitor has completely discharged, and means for rendering conductive said second gate controlled thyristor for conduction during the intervals when the instantaneous full wave rectified line voltage is below the predetermined unidirectional output voltage.

Claim 10

A power circuit according to claim 7 wherein said predetermined rectifier terminal is the positive rectifier output terminal, the circuit coupled between said rectifier output terminals further includes a diode connected between said positive rectifier output terminal and filter capacitor, and said second gate controlled thyristor is connected between said positive rectifier output terminal and a junction between said filter capacitor and first gate controlled thyristor.

Claim 11

A power circuit according to claim 7 wherein the circuit coupled between said rectifier output terminals further includes an inductor in series between said filter capacitor and first gate controlled thyristor, and said means for rendering conductive said first gate controlled thyristor effects resonant charging of said filter capacitor by delaying gating until near the peak rectified line voltage.

Claim 12

A power circuit according to claim 7 wherein said second gate controlled thyristor is connected between one rectifier input terminal and a junction between said filter capacitor and first gate controlled thyristor, and said means for controlling discharge of said filter capacitor further includes a third gate controlled thyristor connected between the other rectifier input terminal and the junction between said filter capacitor and first gate controlled thyristor.

Claim 13

A power circuit according to claim 7 wherein said means for controlling discharge of said filter capacitor further includes a pair of diodes respectively connected to said pair of rectifier input terminals, said second gate controlled thyristor being connected to each of said diodes and to a junction between said filter capacitor and first gate controlled thyristor.

Claim 14

A power circuit according to claim 7 wherein said means for rendering conductive said second gate controlled thyristor includes voltage sensor means for sensing the instantaneous full wave rectified line voltage and generating a sensor signal indicative thereof, and means for comparing said sensor signal to a reference voltage representative of the predetermined unidirectional output voltage and generating a gating pulse supplied to said second gate controlled thyristor, and said means for rendering conductive said first gate controlled thyristor includes current sensor means and a delay circuit actuated by the resumption of current flow after said filter capacitor has completely discharged.