Abstract A hybrid sample data filter system using quantized data of an analog signal obtained from a delta modulator. A shift register having N preselected taps is fed by the delta modulator. Each of the N taps are fed to a series of AND gates corresponding to the R stages of a coefficient counter and between the stages of the coefficient counter and the AND gates are coefficient setting switches set in accordance with the predetermined weighting of the output taps of the shift register. A ring counter having N stages is also fed to the AND gates for time mutliplexing with each of the stages of the ring counter feeding those AND gates that are fed by the corresponding tap of the shift register. Each of the AND gates fed by the same stage of the R stage coefficient counter is combined in one of a series of N-input OR gates, the output of which is fed to a R-input digital-to-analog converter. A demodulating filter is then connected to the output of the digital-to-analog filter.
A hybrid sample data filter comprising: a. a clock; b. a delta modulator pulsed by the clock; c. a shift register having N output taps and being fed by the delta modulator and being pulsed by the clock; d. a coefficient counter pulsed by the clock and having R output stages; e. a plurality of means for multiplying each of the N outputs of the shift register with each of the R outputs of the coefficient counter; f. a plurality of R OR gates fed by the plurality of multiplying means with each of the R OR gates having N inputs; g. a digital-to-analog converter fed by the plurality of OR gates; and h. a demodulator fed by the digital-to-analog converter.
Claim 2
Dependent Claim
121 words
A hybrid sample data filter comprising: a. a clock; b. a delta modulator pulsed by the clock; c. a shift register having N output taps and being fed by the delta modulator and being pulsed by the clock; d. a coefficient counter pulsed by the clock and having R output stages; e. a plurality of means for multiplying each of the N outputs of the shift register with each of the R outputs of the coefficient counter; f. a plurality of R OR gates fed by the plurality of multiplying means with each of the R OR gates having N inputs; g. a digital-to-analog converter fed by the plurality of OR gates; and h. a demodulator fed by the digital-to-analog converter.
Claim 3
Dependent Claim
21 words
A hybrid sample data filter according to claim 1 wherein the plurality of multiplying means comprises a plurality of AND gates.
Claim 4
Dependent Claim
56 words
A hybrid sample data filter according to claim 2 which further comprises means for time multiplexing the outputs of the plurality of AND gates, the time multiplexing means including a ring counter having N stages with one each of the stages being fed to one each of the AND gates and being pulsed by the clock.
Claim 5
Dependent Claim
33 words
A hybrid sample data filter according to claim 3 which further comprises a plurality of switches one each interposed between the output stages of the coefficient counters and the plurality of AND gates.