US3986047A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ramp release and reset circuit for a three phase voltage regulator
Assignee: International Business Machines Corp
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Filing: 1975-12-22
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Granted: 1976-10-12
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Expires: 1995-12-22
Abstract
Abstract An improved ramp control circuit is provided for use in a three phase, SCR phase controlled, voltage regulator. Two, 180° out of phase timing pulses are generated in a pair of comparators for each phase of the three phase input to the system. The comparator switching point is raised above the zero crossover point on each phase input by a voltage offset associated with each comparator. A logical circuit is driven by the predetermined combinations of the 180° out of phase timing pulses from each of the pair of comparators to produce ramp timing pulses at each output of the logic circuit in accordance with the logic in the logical circuit. Each ramp timing pulse is utilized to generate a linear ramp, released and reset by the beginning and end, respectively, of each of said ramp timing pulses.
Inventors
- 👤 Roy K. Griess
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:33
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/12; G05F1/40; G05F1/44; G05F1/45; H; H02; H02M; H02M1/00; H02M1/08; H02M1/084; H03; H03K; H03K4/00; H03K4/06; H03K4/08; H03K4/48; H03K4/50
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
144 words
A ramp release and reset circuit for a three phase system comprising: a pair of comparators for each phase of the three phase input to the system for generating two, 180° out of phase timing pulses for each phase; a voltage offset means associated with each comparator which raises the comparator switching point above the zero crossover point on each phase input; a logic circuit driven by predetermined combinations of the 180° out of phase timing pulses from each of said pair of comparators to produce output timing pulses at each output of said logic circuit in accordance with the logic in said logic circuit; linear ramp generators, one associated with each of said logic circuit outputs to generate linear ramps released and reset by the beginning and end, respectively, of each of said output timing pulses from each of said logic circuit outputs.
Claim 2
Dependent Claim
144 words
A ramp release and reset circuit for a three phase system comprising: a pair of comparators for each phase of the three phase input to the system for generating two, 180° out of phase timing pulses for each phase; a voltage offset means associated with each comparator which raises the comparator switching point above the zero crossover point on each phase input; a logic circuit driven by predetermined combinations of the 180° out of phase timing pulses from each of said pair of comparators to produce output timing pulses at each output of said logic circuit in accordance with the logic in said logic circuit; linear ramp generators, one associated with each of said logic circuit outputs to generate linear ramps released and reset by the beginning and end, respectively, of each of said output timing pulses from each of said logic circuit outputs.
Claim 3
Dependent Claim
31 words
A ramp release and reset circuit according to claim 1, wherein said logic circuit contains three parallel sections having identical logic functions, one for each phase of the three phase input.
Claim 4
Dependent Claim
90 words
A ramp release and reset circuit according to claim 2, wherein said three parallel sections of said logic circuit each perform the same predetermined logic function, the first section performs the function on the two, 180° out of phase timing pulses for the first and second phase, the second section performs the function on the two, 180° out of phase timing pulses for the second and third phases and the third section performs the function on the two, 180° out of phase timing pulses for the third and first phase.
Claim 5
Dependent Claim
84 words
A ramp release and reset circuit according to claim 3, wherein each parallel section of said logic circuit includes a pair of invert circuits, one for each 180° out of phase timing pulse from the associated pair of comparators, a pair of NAND circuits for logically combining the output of one of said invert circuits with one of the out of phase timing pulses from the next successive phase and a further NAND circuit for combining the outputs of said pair of NAND circuits.
Claim 6
Dependent Claim
68 words
A ramp release and reset circuit according to claim 3, wherein the first section of said three parallel sections of said logic circuit forms the logic functions according to the equation AB.BC + BA.CB wherein AB and BA represent the two, 180° out of phase timing pulses for the first phase and BC and CB represent the two, 180° out of phase timing pulses for the second phase.
Claim 7
Dependent Claim
68 words
A ramp release and reset circuit according to claim 5, wherein the second section of said three parallel sections of said logic circuit performs the logic function according to the equation BC.CA + CB.AC wherein BC and CB represent the two, 180° out of phase timing pulses for the second phase and CA and AC represent the two, 180° out of phase timing pulses for the third phase.
Claim 8
Dependent Claim
68 words
A ramp release and reset circuit according to claim 6, wherein the third section of said three parallel sections of said logic circuit performs the logic function according to the equation CA.AB + AC.BA wherein CA and AC represent the two 180° out of phase timing pulses for the third phase and AB and BA represent the two, 180° out of phase timing pulses for the first phase.
Claim 9
Dependent Claim
59 words
A ramp release and reset circuit according to claim 1, wherein said output timing pulses for each logic circuit output generated according to said predetermined logic function have a rising edge and a falling edge determined in accordance with the input phase wave crossing said offset voltage on the positive side of said wave as it approaches zero crossover.
Claim 10
Dependent Claim
40 words
A ramp release and reset circuit according to claim 1, wherein said linear ramp generator, one associated with each of said logic circuit outputs, is released at approximately 12° prior to ZCO and resets at approximately 108° to prevent overlap.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-10-12 | 1980-04-12 | 1980-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-10-12 | 1984-04-12 | 1984-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-10-12 | 1988-04-12 | 1988-10-12 | $7700.00 | Window Closed / Lapsed |