Common control constant shift reframe circuit

Claim 2

In a time division multiplex system wherein a plurality of digital groups of time division multiplexed channels are time multiplexed together onto a common transmission link, each digital group including a similar predetermined framing bit pattern; a reframer circuit comprising means for storing a given number (m) of selected data bits of each digital group and for cyclically reading the m data bits of each digital group out of store in time coincidence with the appearance of each digital group on said common bus, comparator means serving to compare the output of said means with m data bits of the same digital group that occur one or more frames later in time, suitability storage means for recording for each digital group which of the compared m data bits have had framing pattern violations and which appears as a suitable candidate for the framing bit, shift decoder means coupled to the output of said comparator means and said suitability storage means and serving to search for the framing bit within a window defined by the m bits until it has determined that all m bits are unsuitable or that the true framing bit is within the window, means for loading m new bits into the first recited means and for initializing the suitability storage means for the new m bits when all m bits within said window are unsuitable, and means for shifting the multiplexed data bits of an out-of-frame digital group from one to m bit positions in response to determinative signals from said shift decoder means.

Claim 3

A reframer circuit as defined in claim 1 wherein the number m is selected to provide a predetermined reframe time statistic.

Claim 4

A reframer circuit as defined in claim 2 wherein m = 8.

Claim 5

A reframer circuit as defined in claim 1 wherein the first recited means and the suitability storage means each includes a shared recirculating memory.

Claim 6

A reframer circuit as defined in claim 4 wherein each shared recirculating memory comprises shift registers that are clocked in time coincidence with the appearance of the digital groups on the multiplexed transmission link.

Claim 7

A reframer circuit as defined in claim 5 wherein each of the shift registers comprises a number of cells that exceed by one the number of multiplexed digital groups.

Claim 8

A reframer circuit as defined in claim 1 wherein m new bits are repeatedly loaded into the first recited means and the suitability storage means is repeatedly initialized for the new m bits until the true framing bit is located within said window.

Claim 9

A reframer circuit as defined in claim 1 including means for compensating the reframer circuit for framing pattern changes introduced into each of the multiplexed digital groups during reframing and those introduced by the multiplex system for synchronization purposes.

Claim 10

In a time division multiplex system wherein a plurality of digital groups of time division multiplexed channels are time multiplexed together onto a common bus, each digital group including a similar predetermined framing bit pattern; a common control, constant shift, reframe circuit comprising means including a shared recirculating memory for successively storing m selected data bits of each digital group for framing comparison purposes, comparator means serving to compare successively the stored m bits of said means with m data bits of the same digital group which occur an integral number of frames later in time, suitability storage means including a shared recirculating memory for recording for each digital group which of the data bits that have been compared have had framing pattern violations and which appears as a suitable candidate for the framing bit, shift decoder means coupled to the output of said comparator means and said suitability storage means and serving to search for the framing bit for each digital group within an m-bit window until it has determined that all m bits are unsuitable or that the true framing bit is within the m-bit window, means for loading m new bits into the first recited means and for initializing the suitability storage means for the new m bits when all m bits within said window are unsuitable, and means for shifting the multiplexed data bits of an out-of-frame digital group from one to m bit positions in response to determinative signals from said shift decoder means.

Claim 11

In a time division multiplex system wherein a plurality of digital groups of time division multiplexed channels are time multiplexed together onto a common bus, each digital group including a similar predetermined framing bit pattern; a common control, constant shift, reframe circuit comprising means including a shared recirculating memory for successively storing m selected data bits of each digital group for framing comparison purposes, comparator means serving to compare successively the stored m bits of said means with m data bits of the same digital group which occur an integral number of frames later in time, suitability storage means including a shared recirculating memory for recording for each digital group which of the data bits that have been compared have had framing pattern violations and which appears as a suitable candidate for the framing bit, shift decoder means coupled to the output of said comparator means and said suitability storage means and serving to search for the framing bit for each digital group within an m-bit window until it has determined that all m bits are unsuitable or that the true framing bit is within the m-bit window, means for loading m new bits into the first recited means and for initializing the suitability storage means for the new m bits when all m bits within said window are unsuitable, and means for shifting the multiplexed data bits of an out-of-frame digital group from one to m bit positions in response to determinative signals from said shift decoder means.

Claim 12

A common control reframe circuit as defined in claim 9 wherein the number m is of a magnitude sufficient to achieve a predetermined reframe time statistic.

Claim 13

A common control reframe circuit as defined in claim 10 wherein m = 8.

Claim 14

A common control reframe circuit as defined in claim 9 wherein the shared recirculating memories comprise shift registers that are clocked in time coincidence with the appearance of the digital groups on the common bus.

Claim 15

A common control reframe circuit as defined in claim 12 wherein each of the shift registers comprises a number of cells that exceed by one the number of multiplexed digital groups.

Claim 16

A common control reframe circuit as defined in claim 9 wherein m new data bits are repeatedly loaded into the first recited means and the suitability storage means is repeatedly initialized for the new m bits until the true framing bit of a digital group is located within the m-bit window.

Claim 17

A common control reframe circuit as defined in claim 9 including means for compensating the reframe circuit for framing pattern changes introduced into each of the multiplexed digital groups during reframing and those introduced by the multiplex system for synchronization purposes.

Claim 18

A common control reframe circuit as defined in claim 9 wherein the framing bits are positioned in every other frame of each digital group and the first recited means stores the selected data bits of each digital group for two frames for framing comparison purposes, the comparator means thereby serving to compare for each digital group m data bits which are two frames apart.

Claim 19

A common control reframe circuit as defined in claim 9 wherein five digital groups are multiplexed on to a common bus, said reframe circuit serving to maintain frame synchronization for each of said five digital groups and a test group concurrently in the same time frame.

Claim 20

A common control, constant shift, reframe circuit for maintaining frame synchronization, concurrently in the same time frame, for each of a plurality of digital groups which are time division multiplexed together onto a common bus, each digital group including a plurality of time division multiplexed channels and a similar predetermined framing bit pattern, said reframe circuit comprising data store means including a shared memory for successively storing a given number (m) of selected data bits of each digital group for frame comparison purposes, said data bits of each digital group being read out of said memory in time coincidence with the appearance of each digital group on said common bus, comparator means serving to successively compare the data output of said shared memory with m data bits of the same digital group which occur an exact number of frames later in time, suitability storage means including a shared memory for recording for each digital group which of the m data bits that have been compared have had framing pattern violations and which appears as a suitable candidate for the framing bit, shift decoder means coupled to the output of said comparator means and said suitability storage means and serving to search for the framing bit of an out-of-frame digital group until it has determined that all m bits are unsuitable or that the true framing bit is within the current set of m bits, means for loading m new bits into the data store means and for initializing the suitability storage means for the new m bits and for shifting the multiplexed data bits of an out-of-frame digital group m bit positions when all the m bits of the current m-bit set are unsuitable, and means for shifting the multiplexed data bits of an out-of-frame digital group from one to m bit positions in response to a signal from said shift decoder means indicating the position of the recovered framing bit within the m-bit set.

Claim 21

A common control, constant shift, reframe circuit for maintaining frame synchronization, concurrently in the same time frame, for each of a plurality of digital groups which are time division multiplexed together onto a common bus, each digital group including a plurality of time division multiplexed channels and a similar predetermined framing bit pattern, said reframe circuit comprising data store means including a shared memory for successively storing a given number (m) of selected data bits of each digital group for frame comparison purposes, said data bits of each digital group being read out of said memory in time coincidence with the appearance of each digital group on said common bus, comparator means serving to successively compare the data output of said shared memory with m data bits of the same digital group which occur an exact number of frames later in time, suitability storage means including a shared memory for recording for each digital group which of the m data bits that have been compared have had framing pattern violations and which appears as a suitable candidate for the framing bit, shift decoder means coupled to the output of said comparator means and said suitability storage means and serving to search for the framing bit of an out-of-frame digital group until it has determined that all m bits are unsuitable or that the true framing bit is within the current set of m bits, means for loading m new bits into the data store means and for initializing the suitability storage means for the new m bits and for shifting the multiplexed data bits of an out-of-frame digital group m bit positions when all the m bits of the current m-bit set are unsuitable, and means for shifting the multiplexed data bits of an out-of-frame digital group from one to m bit positions in response to a signal from said shift decoder means indicating the position of the recovered framing bit within the m-bit set.