CMOS Schmitt trigger

Claim 2

In a method for employing CMOS transistors for deriving a transfer function having hysteresis, the steps of: coupling the drain electrode of a p channel MOS transistor, having gate, source and drain electrodes, to the drain electrode of an adjacent n channel MOS transistor, having gate, source and drain electrodes, to form a circuit node at the coupling of said two drain electrodes on which the hysteresis output signal is to be derived; coupling the gates of said coupled p and n channel MOs transistors together to receive the input signal and for applying the input signal in parallel to said p and n channel MOS transistors for comparison with potentials to be established on said source electrodes of said p and n channel transistors to derive the output signal having a high or low state; coupling a first trip point reference signal as a function of the state of the output signal into said source electrode of one of said p and n channel transistors for comparison with the input signal applied to said gates of said n and p channel transistors for establishing a first trip point for the output signal; and coupling a second trip point reference potential onto said source electrode of the other one of said p and n channel transistors for comparison with the input signal for establishing hysteresis in the transfer function of said coupled transistors depending upon whether the output is positive going or negative going.

Claim 3

The method of claim 1 wherein the step of coupling the second trip point reference signal to the source electrode of said other transistor comprises, coupling said second trip point reference signal to said source electrode as a function of the state of said output signal.

Claim 4

The method of claim 1 including the step of, amplifying the output signal and feeding back a portion thereof as positive feedback to said output circuit node for stabilizing the output signal on said output node.

Claim 5

In a CMOS Schmitt trigger: p and n channel type MOS transistor means each having gate, source and drain electrodes and being coupled with their source and drain electrodes in series with each other and with at least one of said p channel MOS transistor means having its drain electrode coupled to said drain electrode of an adjacent n channel MOS transistor means to form a circuit node on which a hysteresis output signal is derived; means for coupling said gate electrodes of said p and n channel MOS transistor means together in parallel with each other to receive an input signal for comparison with potentials established on said source electrodes of said p and n channel MOS transistor means for determining the trip points in said output signal corresponding to switching thereof between a high and a low state; first reference means responsive to the state of said output signal for coupling a first trip point reference signal onto said source electrode of one of said p and n channel MOS transistor means for comparison with said input signal applied to said gates of said p and n channel MOS transistor means for establishing a first trip point for said output; and second reference means for coupling a second trip point reference potential onto said source electrode of the other one of said p and n channel transistor means for comparison with said input signal to establish a second trip point in said output signal which differs from said first trip point depending upon the sign of the change in said input signal.

Claim 6

In a CMOS Schmitt trigger: p and n channel type MOS transistor means each having gate, source and drain electrodes and being coupled with their source and drain electrodes in series with each other and with at least one of said p channel MOS transistor means having its drain electrode coupled to said drain electrode of an adjacent n channel MOS transistor means to form a circuit node on which a hysteresis output signal is derived; means for coupling said gate electrodes of said p and n channel MOS transistor means together in parallel with each other to receive an input signal for comparison with potentials established on said source electrodes of said p and n channel MOS transistor means for determining the trip points in said output signal corresponding to switching thereof between a high and a low state; first reference means responsive to the state of said output signal for coupling a first trip point reference signal onto said source electrode of one of said p and n channel MOS transistor means for comparison with said input signal applied to said gates of said p and n channel MOS transistor means for establishing a first trip point for said output; and second reference means for coupling a second trip point reference potential onto said source electrode of the other one of said p and n channel transistor means for comparison with said input signal to establish a second trip point in said output signal which differs from said first trip point depending upon the sign of the change in said input signal.

Claim 7

The apparatus of claim 4 wherein said second reference means for coupling said second trip point reference signal onto said source electrode of the other one of said p and n channel MOS transistor means couples said second trip point reference signal onto said other one of said transistors as a function of the state of said output signal.

Claim 8

The apparatus of claim 4 wherein said first reference means includes potential divider network means including a third MOS transistor means, having gate, source and drain electrodes, with said gate thereof being responsive to said output signal for applying said first reference signal from said potential divider network means to said source electrode of said one MOS transistor means in response to the state of said output signal.

Claim 9

The apparatus of claim 6 wherein said potential divider network means includes a fourth MOS transistor means of the same channel type as that of said third transistor means and having gate, source and drain electrodes, with said drain of said fourth MOS transistor means being coupled to said source electrode of said thrid MOS transistor means to form a first reference output node therebetween on which is developed said first reference signal to be coupled onto said source electrode of said one transistor means.

Claim 10

The apparatus of claim 7 wherein said second reference means includes, second potential divider network means including a fifth MOS transistor means, having gate, source and drain electrodes, said output signal being coupled to said gate electrode of said fifth MOS transistor means for causing said fifth transistor means to be responsive to said output signal for coupling said second reference signal from said potential divider network means to said source electrode of said other MOS transistor means in response to the state of said output signal, and wherein said second potential divider network means includes a sixth MOS transistor means of the same channel type as that of said fifth transistor means, and having gate, source and drain electrodes, with said drain electrode of said sixth MOS transistor means being coupled to said source electrode of said fifth MOS transistor means to form a second reference output node therebetween on which is developed said second reference signal to be coupled onto said source electrode of said other transistor means.

Claim 11

The apparatus of claim 4 wherein said second reference means includes, potential divider network means including a third MOS transistor means, having gate, source and drain electrodes, said output signal being coupled to said gate electrode of said third MOS transistor means for causing said third transistor means to be responsive to said output signal for coupling said second reference signal from said potential divider network means to said source electrode of said other MOS transistor means in response to the state of said output signal.

Claim 12

The apparatus of claim 9 wherein said potential divider network means includes, a fourth MOS transistor means of the same channel type as that of said third transistor means, and having gate, source and drain electrodes, which said drain electrode of said fourth MOS transistor means being coupled to said source electrode of said third MOS transistor means to form a second reference output node therebetween on which is developed said second reference signal to be coupled onto said source electrode of said other transistor means.