Digital automatic gain control circuit

Claim 2

A digital gain control circuit suitable for use in a digital signal processor such as a digital demodulator comprising: a multiplier for forming the product of an uncontrolled digital input signal and a digital gain control signal; a feedback loop responsive to the magnitude of the output of the said multiplier and a digital reference for generating the said digital gain control signal; said feedback loop including; means for forming an error signal corresponding in magnitude and sign to the difference between the magnitude of the multiplier output and the said reference; accumulator means responsive to said error signal for generating said gain control signal; and a feedback control loop responsive to the sign of the accumulator output for modifying the sign of the reference to cause said error signal to assume alternate negative and positive fixed values when the multiplier output falls to zero for a predetermined period of time.

Claim 3

A digital gain control circuit as set forth in claim 1 in which said means for forming an error signal corresponding in magnitude and sign to the difference between the magnitude of the multiplier output and the said reference includes: adder means for forming the algebraic sum of the multiplier output and the output of the said feedback control loop; a second multiplier responsive to the output of said adder means and a second constant for adjusting the error signal magnitude and sign and providing an output for the said accumulator; and said accumulator includes, an adder having one input connected to receive the signal from said second multiplier, a delay circuit connected between the output of the adder and another input whereby the output of the second multiplier is accumulated, a third multiplier connected to the adder output and a constant which is substantially equal to one, and means for converting the third multiplier output to positive magnitudes regardless of sign.

Claim 4

A digital gain control circuit as set forth in claim 2 in which said feedback control loop includes: means responsive to the sign of the output of the third multiplier for providing a first digital value for one sign and a second digital value for the other sign; and a fourth multiplier responsive to said first or second digital value as selected by the sign and a constant for providing the said digital reference.

Claim 5

A digital gain control circuit suitable for use in a digital signal processor such as a digital demodulator comprising: a multiplier for forming the product of an uncontrolled digital input signal and a digital gain control signal; a feedback loop responsive to the square of the output of the said multiplier and a digital reference for generating the said digital gain control signal; said feedback loop including; means for forming an error signal corresponding in magnitude and sign to the difference between the square of the multiplier output and the said reference; accumulator means responsive to said error signal for generating said gain control signal, and a feedback control loop responsive to the sign of the accumulator output for modifying the sign of the reference to cause said error signal to assume alternate negative and positive fixed values when the square of the multiplier output falls to zero for a predetermined period of time.

Claim 6

A digital gain control circuit suitable for use in a digital signal processor such as a digital demodulator comprising: a multiplier for forming the product of an uncontrolled digital input signal and a digital gain control signal; a feedback loop responsive to the square of the output of the said multiplier and a digital reference for generating the said digital gain control signal; said feedback loop including; means for forming an error signal corresponding in magnitude and sign to the difference between the square of the multiplier output and the said reference; accumulator means responsive to said error signal for generating said gain control signal, and a feedback control loop responsive to the sign of the accumulator output for modifying the sign of the reference to cause said error signal to assume alternate negative and positive fixed values when the square of the multiplier output falls to zero for a predetermined period of time.

Claim 7

A digital gain control circuit as set forth in claim 4 in which said means for forming an error signal corresponding in magnitude and sign to the difference between the square of the multiplier output and the said reference includes: adder means for forming the albegraic sum of the square of the multiplier output and the output of the said feedback control loop; a second multiplier responsive to the output of said adder means and a second constant for adjusting the error signal magnitude and sign and providing an output for the said accumulator; and said accumulator includes, an adder having one input connected to receive the signal from said second multiplier, a delay circuit connected between the output of the adder and another input whereby the output of the second multiplier is accumulated, a third multiplier connected to the adder output and a constant which is substantially equal to one, and means for converting the third multiplier output to positive magnitudes regardless of sign.

Claim 8

A digital gain control circuit as set forth in claim 5 in which said feedback control loop includes: means responsive to the sign of the output of the third multiplier for providing a first digital value for one sign and a second digital value for the other sign; and a fourth multiplier responsive to said first or second digital value as selected by the sign and a constant for providing the said digital reference.

Claim 9

A digital gain control circuit suitable for use in a digital signal processor such as a digital demodulator comprising: a multiplier for forming the product of an uncontrolled digital input signal and a digital gain control signal; a feedback loop responsive to the output of said multiplier and a digital reference for generating the said gain control signal; said loop including: means for forming an error signal corresponding in magnitude and sign to the difference between the magnitude of the multiplier output and the said reference, accumulator means responsive to said error signal for generating said gain control signal, a first feedback control loop responsive to the sign of the accumulator output for modifying the sign of the reference to cause said error signal to assume alternate negative and positive fixed values when the multiplier output falls to zero for a predetermined period of time; and a second feedback control loop responsive to the gain control signal for changing the sensitivity of the feedback loop as a function of the gain control signal.

Claim 10

A digital gain control circuit suitable for use in a digital signal processor such as a digital demodulator comprising: a multiplier for forming the product of an uncontrolled digital input signal and a digital gain control signal; a feedback loop responsive to the output of said multiplier and a digital reference for generating the said gain control signal; said loop including: means for forming an error signal corresponding in magnitude and sign to the difference between the magnitude of the multiplier output and the said reference, accumulator means responsive to said error signal for generating said gain control signal, a first feedback control loop responsive to the sign of the accumulator output for modifying the sign of the reference to cause said error signal to assume alternate negative and positive fixed values when the multiplier output falls to zero for a predetermined period of time; and a second feedback control loop responsive to the gain control signal for changing the sensitivity of the feedback loop as a function of the gain control signal.

Claim 11

A digital gain control circuit as set forth in claim 7 in which said means for forming an error signal corresponding in magnitude and sign to the difference between the magnitude of the multiplier output and the said reference includes: adder means for forming the algebraic sum of the multiplier output and the output of the said feedback control loop; a second multiplier responsive to the output of said adder means and a second constant for adjusting the error signal magnitude and sign and providing an output for the said accumulator; a third multiplier responsive to the said gain control signal and said second multiplier output for modifying the output of the second multiplier and sensitivity of the feedback loop as a function of the gain control signal; and said accumulator includes an adder having one input connected to receive the signal from said third multiplier, a delay circuit connected between the output of the adder and another input whereby the output of the third multiplier is accumulated, a fourth multiplier connected to the adder output and a constant which is substantially equal to one, and means for converting the fourth multiplier output to positive magnitudes regardless of sign.

Claim 12

A digital gain control circuit as set forth in claim 8 in which said feedback control loop includes: means responsive to the sign of the output of the fourth multiplier for providing a first digital value for one sign and a second digital value for the other sign; and a fifth multiplier responsive to said first or second digital value as selected by the sign and a constant for providing the said digital reference.

Claim 13

A digital gain control circuit suitable for use in a digital signal processor such as a digital demodulator comprising: a multiplier for forming the product of an uncontrolled digital input signal and a digital gain control signal; a feedback loop responsive to the output of said multiplier and a digital reference for generating the said gain control signal; said loop including: means for forming an error signal corresponding in magnitude and sign to the difference between the square of the multiplier output and the said reference, accumulator means responsive to said error signal for generating said gain control signal, a first feedback control loop responsive to the sign of the accumulator output for modifying the sign of the reference to cause said error signal to assume alternate negative and positive fixed values when the square of the multiplier output falls to zero for a predetermined period of time; and a second feedback control loop responsive to the gain control signal for changing the sensitivity of the feedback loop as a function of the gain control signal.

Claim 14

A digital gain control circuit suitable for use in a digital signal processor such as a digital demodulator comprising: a multiplier for forming the product of an uncontrolled digital input signal and a digital gain control signal; a feedback loop responsive to the output of said multiplier and a digital reference for generating the said gain control signal; said loop including: means for forming an error signal corresponding in magnitude and sign to the difference between the square of the multiplier output and the said reference, accumulator means responsive to said error signal for generating said gain control signal, a first feedback control loop responsive to the sign of the accumulator output for modifying the sign of the reference to cause said error signal to assume alternate negative and positive fixed values when the square of the multiplier output falls to zero for a predetermined period of time; and a second feedback control loop responsive to the gain control signal for changing the sensitivity of the feedback loop as a function of the gain control signal.

Claim 15

A digital gain control circuit as set forth in claim 10 in which said means for forming an error signal corresponding in magnitude and sign to the difference between the square of the multiplier output and the said reference includes: adder means for forming the algebraic sum of the square of the multiplier output and the output of the said feedback control loop; a second multiplier responsive to the output of said adder means and a second constant for adjusting the error signal magnitude and sign and providing an output for the said accumulator; a third multiplier responsive to the said gain control signal and said second multiplier output for modifying the output of the second multiplier and the sensitivity of the feedback loop as a function of the gain control signal; and said accumulator includes an adder having one input connected to receive the signal from said third multiplier, a delay circuit connected between the output of the adder and another input whereby the output of the third multiplier is accumulated, a fourth multiplier connected to the adder output and a constant which is substantially equal to one, and means for converting the fourth multiplier output to positive magnitudes regardless of sign.

Claim 16

A digital gain control circuit as set forth in claim 11 in which said feedback control loop includes: means responsive to the sign of the output of the fourth multiplier for providing a first digital value for one sign and a second digital value for the other sign; and a fifth multiplier responsive to said first or second digital value as selected by the sign and a constant for providing the said digital reference.