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US3980508A Expired / Lapsed US ⏱️ 0.0 years remaining

Process of producing semiconductor device

Assignee: Mitsubishi Electric Corp
•
Filing: 1974-10-01
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Granted: 1976-09-14
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Expires: 1994-10-01
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Abstract

Abstract An SiO 2 film doped with an impurity is formed on at least one portion of a surface of a semiconductor wafer. The wafer is selectively etched after a protective film for selective etching is disposed into a predetermined pattern on the SiO 2 film. The impurity included in the SiO 2 film can be diffused into the wafer to form a PN junction in the latter. Then the wafer is selectively etched until that surface of the wafer to which the PN junction is exposed is bevelled.

Inventors

  • 👤 Saburo Takamiya
  • 👤 Masaharu Hama
  • 👤 Akihiro Kondo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 11:59
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/69; H10P50/691; H10D; H10D62/00; H10D62/10; H10D62/117; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171; H10P50/60; H10P50/64; H10P50/642; Y; Y10; Y10S; Y10S438/00; Y10S438/978

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 137 words
A process of producing a semiconductor device, comprising: a. providing a silicon wafer having a major surface; b. disposing on a portion of said major surface a doped silicon dioxide film, said doped silicon dioxide film being doped with an impurity to impart thereto an etching rate of from about ten to about fifty times the etching rate of silicon; c. disposing on a portion of said doped silicon dioxide film a protective film of etchant resistant material to define an etching mask for protecting portions of said doped silicon dioxide film underlying said protective film, and for protecting the corresponding portions of said major surface which underlie said portions of said doped silicon dioxide underlying said protective film; and d. etching portions of said doped silicon layer and underlying major surface unprotected by said protective film.
Claim 2
Dependent Claim 137 words
A process of producing a semiconductor device, comprising: a. providing a silicon wafer having a major surface; b. disposing on a portion of said major surface a doped silicon dioxide film, said doped silicon dioxide film being doped with an impurity to impart thereto an etching rate of from about ten to about fifty times the etching rate of silicon; c. disposing on a portion of said doped silicon dioxide film a protective film of etchant resistant material to define an etching mask for protecting portions of said doped silicon dioxide film underlying said protective film, and for protecting the corresponding portions of said major surface which underlie said portions of said doped silicon dioxide underlying said protective film; and d. etching portions of said doped silicon layer and underlying major surface unprotected by said protective film.
Claim 3
Dependent Claim 28 words
A process of producing a semiconductor device, according to claim 1, further comprising: diffusing said impurity with which said silicon dioxide film is doped into said silicon wafer.
Claim 4
Dependent Claim 28 words
A process of producing a semiconductor device, according to claim 1, wherein said silicon wafer includes regions of opposite conductivity type forming at least one PN junction therein.
Claim 5
Dependent Claim 93 words
A process of producing a semiconductor device, according to claim 1; wherein said protective film is disposed overlying a portion of said major surface with a portion of said major surface about a periphery of said protective film unprotected; wherein said silicon wafer is etched to form a bevelled surface portion about said protective film and having a perimeter similar to the periphery of said protective film; and wherein said silicon wafer includes regions of opposite conductivity type forming a least one PN junction having a portion exposed at said bevelled surface portion.

References Cited (Backward Citations)

US2975080A Cited
US3179860A Cited
US3575644A Cited
US3713913A Cited
US3669775A Cited
US3842490A Cited
US3767485A Cited
US3825454A Cited
US3769109A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-09-14 1980-03-15 1980-09-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-09-14 1984-03-15 1984-09-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-09-14 1988-03-15 1988-09-14 $7700.00 Window Closed / Lapsed

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