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US3979746A Expired / Lapsed US ⏱️ 0.0 years remaining

High-speed Manchester code demodulator

Assignee: United States Department of the Navy
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Filing: 1975-04-28
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Granted: 1976-09-07
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Expires: 1995-04-28
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Abstract

Abstract A demodulator for decoding the Manchester code is described in which the bit rate is maximized by using a one shot set up for a pulse width less than one-half the bit period. Control of the one-shot is established so that it is clocked at the bit rate but not at twice the bit rate, in order to receive high data rates serially over a single fiber optic channel.

Inventors

  • 👤 Bobby R. Jarrett

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 17:15
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 395 words
A demodulator for decoding the Manchester code at bit rates approaching one gigahertz comprising: a high speed transition marker which receives the Manchester code and generates a pulse representative of the detected zero crossings of both information and phase bits of the Manchester data comprising: a first NOR logic gate receiving at an input thereof the Manchester code and generating at outputs thereof an OR output and a NOR output; means to delay and invert the NOR output of said first gate; a second NOR gate receiving at an input thereof the NOR output of said first gate, at another input the delayed and inverted NOR output of said first gate; means to delay and invert the OR output of said first gate; a third NOR gate receiving at one input the OR output of said first gate and at another input the delayed and inverted OR output of said first gate; and a wire-ORed connection of said outputs of said second and third NOR gates; a high speed edge triggered flip-flop having a clock input, a reset input which overrides the clock input, an ouput and data inputs wired such that when the output signal of said transition marker is presented to the clock input of the flip-flop, the flip-flop is triggered and the output goes high or stays high unless locked out by the reset; time delay means connected between said flip-flop ouput and said reset input whereby the flip-flop output pulse width is less than one half the Manchester bit period and is equal to the time of the delay means and the time of the propagation delay from the reset to the output of said flip-flop, and whereby the flip-flop output down time is equal to the time of the delay means and the time of the propagation delay from the reset to the output and the time of the propagation delay from the clock to the output of said flip-flop and the time till the next clock input pulse, and whereby the reset input is held high by the flip-flop output at the point in time corresponding to the occurrence of the phase pulses of the transition marker thereby locking out said phase clock input pulses; and means to strobe the Manchester code input with the output of said flip-flop such that a conversion from Manchester to NRZ is obtained.
Claim 2
Dependent Claim 395 words
A demodulator for decoding the Manchester code at bit rates approaching one gigahertz comprising: a high speed transition marker which receives the Manchester code and generates a pulse representative of the detected zero crossings of both information and phase bits of the Manchester data comprising: a first NOR logic gate receiving at an input thereof the Manchester code and generating at outputs thereof an OR output and a NOR output; means to delay and invert the NOR output of said first gate; a second NOR gate receiving at an input thereof the NOR output of said first gate, at another input the delayed and inverted NOR output of said first gate; means to delay and invert the OR output of said first gate; a third NOR gate receiving at one input the OR output of said first gate and at another input the delayed and inverted OR output of said first gate; and a wire-ORed connection of said outputs of said second and third NOR gates; a high speed edge triggered flip-flop having a clock input, a reset input which overrides the clock input, an ouput and data inputs wired such that when the output signal of said transition marker is presented to the clock input of the flip-flop, the flip-flop is triggered and the output goes high or stays high unless locked out by the reset; time delay means connected between said flip-flop ouput and said reset input whereby the flip-flop output pulse width is less than one half the Manchester bit period and is equal to the time of the delay means and the time of the propagation delay from the reset to the output of said flip-flop, and whereby the flip-flop output down time is equal to the time of the delay means and the time of the propagation delay from the reset to the output and the time of the propagation delay from the clock to the output of said flip-flop and the time till the next clock input pulse, and whereby the reset input is held high by the flip-flop output at the point in time corresponding to the occurrence of the phase pulses of the transition marker thereby locking out said phase clock input pulses; and means to strobe the Manchester code input with the output of said flip-flop such that a conversion from Manchester to NRZ is obtained.

References Cited (Backward Citations)

US3631269A Cited
US3609569A Cited
US3727202A Cited
US3829853A Cited
US3790821A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-09-07 1980-03-08 1980-09-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-09-07 1984-03-08 1984-09-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-09-07 1988-03-08 1988-09-07 $7700.00 Window Closed / Lapsed

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