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Patent US3979692A successfully refreshed from Google Patents.
US3979692A
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Apparatus for phase keying in frequency and phase voltage controlled oscillator with an incoming signal having a T period, and phase coded of the biphase PCM type or PSK type
Assignee: Thales SA
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Filing: 1975-08-04
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Granted: 1976-09-07
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Expires: 1995-08-04
Abstract
Abstract Apparatus for phase keying in frequency and phase voltage controlled oscillator with an incoming signal having a T period phase coded of the biphase PCM or PSK type. The apparatus comprises a circuit loop for phase controlling the oscillator with logic circuitry and first and second conductive paths. Each of the first and second conductive paths have integrators. The integration time of the first and second integrators is equal to the period T of the incoming signal. The limits of integration of the first integrator are - T/8 and + 7T/8 and the limits of integration of the second integrator are + T/8 and + 9T/8. A delay element is disposed between the logic circuitry and the second conductive path introducing retardation time of T/4.
Inventors
- 👤 Jean-Charles Benoist
- 👤 Francois Bitsch
- 👤 Gerard Rene Joseph Tarel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 01:16
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0332
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
118 words
Apparatus for phase keying in frequency and phase voltage controlled oscillator with an incoming signal having a T period, and phase coded, of the biphase PCM type or PSK type comprising a circuit loop for phase controlling said oscillator with logic circuitry and first and second conductive paths having first and second integrators respectively, the integration time of each of said first and second integrators being equal to the period T of the incoming signal, the limits of integration time of said first integrator being -T/8 and +7T/8 and that of said second integrator being +T/8 and +9T/8, and a delay element interposed between the logic circuitry and said second conductive path for introducing retardation time of T/4.
Claim 2
Dependent Claim
118 words
Apparatus for phase keying in frequency and phase voltage controlled oscillator with an incoming signal having a T period, and phase coded, of the biphase PCM type or PSK type comprising a circuit loop for phase controlling said oscillator with logic circuitry and first and second conductive paths having first and second integrators respectively, the integration time of each of said first and second integrators being equal to the period T of the incoming signal, the limits of integration time of said first integrator being -T/8 and +7T/8 and that of said second integrator being +T/8 and +9T/8, and a delay element interposed between the logic circuitry and said second conductive path for introducing retardation time of T/4.
Claim 3
Dependent Claim
41 words
Apparatus according to claim 1, further comprising a third conductive path for bit detection having a third integrator, and another delay element interposed between the logic circuitry and said third conductive path, said other delay element introducing retardation time of T/8.
Claim 4
Dependent Claim
43 words
Apparatus according to claim 2, further comprising a fourth conductive path for rapid acquisition, switching means being arranged at the input of the oscillator to put the oscillator in the phase controlling circuit loop with two parallel conductive paths thereby eliminating phase ambiguity.
Claim 5
Dependent Claim
26 words
Apparatus according to claim 3, further comprising a third delay element introducing retardation time of T/4 interposed between said logic circuitry and said fourth conductive path.
Claim 6
Dependent Claim
59 words
Apparatus according to claim 1, further comprising a third conductive path for bit detection having a third integrator, said third conductive path being connected directly to said logic circuitry without introducing time retardation, a fourth conductive path for rapid acquisition, and a delay element interposed between said logic circuitry and said fourth conductive path introducing retardation time of 3T/8.
References Cited (Backward Citations)
US3806815A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-09-07 | 1980-03-08 | 1980-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-09-07 | 1984-03-08 | 1984-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-09-07 | 1988-03-08 | 1988-09-07 | $7700.00 | Window Closed / Lapsed |