Transistor amplifier of the Darlington type with internal bias providing low offset voltage and offset current drift

Claim 2

In a transistor amplifier of the Darlington type in which two successive transistors are connected with their collectors in common and with the emitter of the first transistor supplying current to the base of the second transistor to thereby form a three terminal device in which a first terminal provides a connection to apply an input signal to the base of the first transistor, and in which a second terminal at the common connection of the collectors of said transistors and a third terminal at the emitter of the second transistor provide connections to apply the output current of the device, the improvement which comprises: transistor means having base and emitter portions connected in common with the base and emitter of the second transistor, and having a collector portion connected to the emitter of the first transistor to direct through the first transistor a bias current which is a predetermined fraction of the collector current of the second transistor, and the input impedance between the first and third terminals of the device being that presented by the base-to-emitter impedance of the first transistor operated at the bias current level determined by said transistor means, in series with the impedance presented between the emitter of the first transistor and the third terminal; whereby the three terminal device will present a substantial input impedance to a signal source connected to said first terminal to avoid loading the source and to minimize the amount of current needed to drive the device, and at the same time will provide a highly predictable relationship between input voltage at said first terminal and output current through said second and third terminals.

Claim 3

A transistor amplifier of the Darlington type as claimed in claim 1 wherein said transistor means is a third transistor having base, collector and emitter portions separate from the base, collector and emitter of the second transistor.

Claim 4

A transistor amplifier of the Darlington type as claimed in claim 1 wherein the transistor means and the second transistor together form a double collector transistor with the base and emitter portions of the transistor means coinciding respectively with the base and emitter of the second transistor, and with the collector portion of the transistor means being formed as a separate collector connected to the emitter of the first transistor.

Claim 5

A transistor amplifier of the Darlington type as claimed in claim 3 wherein the double collector transistor forming the transistor means and the second transistor is a lateral PNP integrated circuit transistor.

Claim 6

A transistor amplifier of the Darlington type as claimed in claim 1 wherein said transistor means and said second transistor have a ratio of collector areas corresponding to said predetermined fraction.

Claim 7

A transistor amplifier of the Darlington type as claimed in claim 1 wherein the predetermined fraction of the collector current of the second transistor which is produced by the current producing means is less than one half.

Claim 8

A transistor amplifier of the Darlington type as claimed in claim 6 wherein said predetermined fraction is within the range of approximately one eighth to one fifteenth.

Claim 9

A transistor amplifier of the Darlington type as claimed in claim 1 wherein said predetermined fraction is related to the current gain of the first transistor such that the inverse of the fraction lies within the range of approximately one third to one tenth of the value of the current gain of the first transistor.

Claim 10

In an active load for a differential pair arrangement wherein the active load comprises two matched Darlington-type amplifiers, each having two successive transistors connected with their collectors in common and with the emitter of the first transistor connected to the base of the second transistor to thereby form a three terminal device in which a first terminal provides a connection to apply a signal to the base of the first transistor, and in which a second terminal at the common connection of the collectors of said transistors and a third terminal at the emitter of the second transistor provide connections to apply the output current of the device to the differential pair arrangement, the improvement which comprises: in each of the two Darlington-type devices, a transistor means having emitter and base portions in common with the emitter and base of the second transistor, and having a collector portion connected to the emitter of the first transistor to direct through the first transistor a bias current which is a predetermined fraction of the collector current of the second transistor, the two transistor means in the two Darlington-type devices being matched to provide the same bias currents, the impedance between the first and third terminals of each of the two Darlington-type devices being that presented by the base-to-emitter impedance of the first transistor operated at the bias current level determined by said transistor means, in series with the impedance presented between the emitter of the first transistor and the third terminal, and a constant voltage source connected to the first terminals of each of the two Darlington-type devices, whereby each of the three terminal devices will present a substantial impedance to the voltage source connected to said first terminals to avoid loading the source and to minimize the amount of current needed to drive the devices, and at the same time will provide a highly predictable relationship between the input voltage at said first terminals and the output currents applied through said second and third terminals to the differential pair arrangement.

Claim 11

In an active load for a differential pair arrangement wherein the active load comprises two matched Darlington-type amplifiers, each having two successive transistors connected with their collectors in common and with the emitter of the first transistor connected to the base of the second transistor to thereby form a three terminal device in which a first terminal provides a connection to apply a signal to the base of the first transistor, and in which a second terminal at the common connection of the collectors of said transistors and a third terminal at the emitter of the second transistor provide connections to apply the output current of the device to the differential pair arrangement, the improvement which comprises: in each of the two Darlington-type devices, a transistor means having emitter and base portions in common with the emitter and base of the second transistor, and having a collector portion connected to the emitter of the first transistor to direct through the first transistor a bias current which is a predetermined fraction of the collector current of the second transistor, the two transistor means in the two Darlington-type devices being matched to provide the same bias currents, the impedance between the first and third terminals of each of the two Darlington-type devices being that presented by the base-to-emitter impedance of the first transistor operated at the bias current level determined by said transistor means, in series with the impedance presented between the emitter of the first transistor and the third terminal, and a constant voltage source connected to the first terminals of each of the two Darlington-type devices, whereby each of the three terminal devices will present a substantial impedance to the voltage source connected to said first terminals to avoid loading the source and to minimize the amount of current needed to drive the devices, and at the same time will provide a highly predictable relationship between the input voltage at said first terminals and the output currents applied through said second and third terminals to the differential pair arrangement.

Claim 12

An active load for a differential pair arrangement as claimed in claim 9 wherein, in each Darlington-type device, the transistor means and the second transistor together form a double collector integrated circuit PNP transistor with the base and emitter portions of the transistor means coinciding respectively with the base and emitter of the second transistor, and with the collector portion of the transistor means being formed as a separate collector connected to the emitter of the first transistor.

Claim 13

An active load for a differential pair arrangement as claimed in claim 9 wherein said predetermined fraction of the collector current of the second transistor which is produced by the transistor means is within the range of approximately one-eighth to one-fifteenth.

Claim 14

An active load for a differential pair arrangement as claimed in claim 9 wherein said predetermined fraction is related to the current gain of the first transistor such that the inverse of the fraction lies within the range of approximately one-third to one-tenth of the value of the current gain of the first transistor.