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US3977019A
Expired / Lapsed
US
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Semiconductor integrated circuit
Assignee: Sony Corp
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Filing: 1974-05-14
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Granted: 1976-08-24
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Expires: 1994-05-14
Abstract
Abstract A semiconductor integrated circuit, in which an isolation region with one conductivity type and a plurality of island regions with another conductivity type separated by the isolation region are provided, is disclosed. In this case, a high resistance polycrystalline semiconductor layer is formed to cover whole of a surface portion of a PN-junction formed between the isolation region and the island regions.
Inventors
- 👤 Takeshi Matsushita
- 👤 Yoshiyuki Kawana
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:00
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/118; H10D84/00; H10D84/60; H10D84/641; H10D84/642; H10D88/00; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/085; Y10S148/122; Y10S148/125
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
153 words
A semiconductor integrated circuit comprising: a. a substrate of first conductivity type; b. a first island region of second conductivity type formed on said substrate and having a first voltage potential applied thereto; c. a second island region of second conductivity type formed on said substrate and having a second voltage potential applied thereto; d. an isolation region of first conductivity type between said first and second regions and having first and second interfaces therewith, first and second PN junctions being formed by said first and second interfaces, respectively; and e. a polycrystalline resistance layer doped to achieve a predetermined resistance sufficient to suppress formation of a reverse region in the isolation region, said resistance region being continuously formed in contact with said first and second island regions, isolation region, and first and second PN junctions to create a voltage gradient across said resistance layer due to said first and second voltage potentials.
Claim 2
Dependent Claim
153 words
A semiconductor integrated circuit comprising: a. a substrate of first conductivity type; b. a first island region of second conductivity type formed on said substrate and having a first voltage potential applied thereto; c. a second island region of second conductivity type formed on said substrate and having a second voltage potential applied thereto; d. an isolation region of first conductivity type between said first and second regions and having first and second interfaces therewith, first and second PN junctions being formed by said first and second interfaces, respectively; and e. a polycrystalline resistance layer doped to achieve a predetermined resistance sufficient to suppress formation of a reverse region in the isolation region, said resistance region being continuously formed in contact with said first and second island regions, isolation region, and first and second PN junctions to create a voltage gradient across said resistance layer due to said first and second voltage potentials.
Claim 3
Dependent Claim
23 words
The integrated circuit of claim 1 in which said polycrystalline semiconductor resistance layer has a resistivity of 2.5 × 10 4 ohm cm.
Claim 4
Dependent Claim
224 words
A semiconductor integrated darlington circuit comprising: a. a substrate of first conductivity type as a common collector; b. a first island region as a first base of second conductivity type formed on said substrate and having a first voltage potential applied thereto; c. a first emitter region of first conductivity type formed in said first island region; d. a second island region as a second base of second conductivity type formed on said substrate and having a second voltage potential applied thereto; e. a second emitter region of first conductivity type formed in said second island region; f. an isolation region of first conductivity type between said first and second regions and having first and second interfaces therewith, first and second PN junctions being formed by said first and second interfaces, respectively; g. a polycrystalline resistance layer doped to achieve a predetermined resistance sufficient to suppress formation of a reverse region in the isolation region, said resistance layer being continuously formed in contact with said first and second island region, isolation region, and first and second PN junctions to create a voltage gradient across said resistance layer due to said first and second voltage potentials; h. an insulating layer over said resistance layer; and i. a metal layer over said insulating layer, said metal layer being connected to said first emitter and second base.
Claim 5
Dependent Claim
224 words
A semiconductor integrated darlington circuit comprising: a. a substrate of first conductivity type as a common collector; b. a first island region as a first base of second conductivity type formed on said substrate and having a first voltage potential applied thereto; c. a first emitter region of first conductivity type formed in said first island region; d. a second island region as a second base of second conductivity type formed on said substrate and having a second voltage potential applied thereto; e. a second emitter region of first conductivity type formed in said second island region; f. an isolation region of first conductivity type between said first and second regions and having first and second interfaces therewith, first and second PN junctions being formed by said first and second interfaces, respectively; g. a polycrystalline resistance layer doped to achieve a predetermined resistance sufficient to suppress formation of a reverse region in the isolation region, said resistance layer being continuously formed in contact with said first and second island region, isolation region, and first and second PN junctions to create a voltage gradient across said resistance layer due to said first and second voltage potentials; h. an insulating layer over said resistance layer; and i. a metal layer over said insulating layer, said metal layer being connected to said first emitter and second base.
Claim 6
Dependent Claim
41 words
The circuit of claim 3 in which a polycrystalline resistance layer is formed in contact over a PN junction between said first emitter region and first island region and a PN junction between said second emitter region and second island region.
References Cited (Backward Citations)
US3725150A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-24 | 1980-02-23 | 1980-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-24 | 1984-02-23 | 1984-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-24 | 1988-02-23 | 1988-08-24 | $7700.00 | Window Closed / Lapsed |