Level shifting circuit device

Claim 2

A level shifting circuit device comprising a first terminal connected to a high amplitude power source, an output terminal, a first conductive path formed between said first terminal and said output terminal which includes a first IG-FET of one conductive channel type whose first electrode is connected to said first terminal, means for applying a first pulse signal to said first IG-FET, a reference voltage input terminal, a second conductive path formed between said reference voltage input terminal and said output terminal so as to include a second IG-FET of the other conductive channel type, means for generating a second pulse signal of sepcified polarity substantially synchronized with said first pulse signal, and a circuit arrangement for rendering said second IG-FET conductive when said second pulse signal has coincided with a low amplitude logic signal from a logic circuit immediately preceding said level shifting circuit device, wherein only when said second pulse signal and said logic signal have coincided with each other, a reference voltage output is obtained; and except for said time a high amplitude output is obtained through said first conductive path.

Claim 3

A level shifting circuit device according to claim 1, wherein said first conductive path includes said first IG-FET whose source and drain electrodes are connected between said first terminal and said output terminal; said second conductive path includes said second IG-FET whose drain and source electrodes are connected between said output terminal and said reference voltage input terminal; and said circuit arrangement includes means for applying a specified voltage to the gate electrode of said second IG-FET, a gate circuit whose output terminal is connected to said reference voltage input terminal, and means for supplying said second pulse signal and said low amplitude logic signal to the input terminals of said gate circuit.

Claim 4

A level shifting circuit device according to claim 1, wherein said second conductive path further includes a fourth IG-FET of said other conductive channel type connected in series to said second IG-FET and between said output terminal and said reference voltage input terminal; and said circuit arrangement includes means for applying said low amplitude logic signal commonly to the gate electrodes of said third IG-FET and second IG-FET, means for applying said second pulse signal to the gate electrode of said fourth IG-FET, and means for grounding said reference voltage input terminal.

Claim 5

A level shifting circuit device according to claim 1, wherein said first conductive path includes said first IG-FET whose source and drain electrodes are connected between said first terminal and said output terminal; said second conductive path includes parallel-series logic circuit having a plurality of IG-FET's of said other conductive channel type connected in series between said output terminal and said reference voltage input terminal; and said circuit arrangement includes means for applying said second pulse signal to the gate electrode of said third IG-FET, means for applying first, second, third and fourth logic signals VI 11, VI 12, VI 21 and VI 22 to the gate electrodes of said plurality of IG-FET's, respectively, there being established between said low amplitude logic signals VI 11, VI 12, VI 21 and VI 22 and said logic signal VI a relation expressed by the logical formula: VI = VI 11 .sup.. VI 12 + VI 21 .sup.. VI 22, and said means for grounding said reference voltage input terminal.

Claim 6

A level shifting circuit device according to claim 3, further comprising at least one of a storage circuit for storing an output signal from said level shifting circuit device and a stabilizer circuit for stabilizing in terms of logic level an output from said storage circuit.

Claim 7

A level shifting circuit device according to claim 5, wherein said storage circuit includes a storage output terminal, fifth and sixth IG-FET's of said one conductive channel type connected in series between said storage output terminal and said first terminal, and seventh and eighth IG-FET's of said other conductive channel type connected in series between said storage output terminal and said reference voltage input terminal, the gate electrodes of said sixth and seventh IG-FET's being connected to said output terminal, the gate electrode of said fifth IG-FET being supplied with a signal having a polarity opposite to that of said second pulse signal, the gate electrode of said eighth IG-FET being supplied with said second pulse signal; and said stabilizer circuit includes ninth and tenth IG-FET's of said one conductive channel type connected in series between said first terminal and said storage output terminal, eleventh and twelfth IG-FET's of said other conductive channel type connected in series between said storage output terminal and said reference voltage input terminal, means for connecting commonly the gate electrodes of said tenth and eleventh IG-FET's, a thirteenth IG-FET of said one conductive channel type connected between said commonly connecting point and said first terminal, a fourteenth IG-FET of said other conductive channel type connected between said commonly connecting point and said reference voltage input terminal, means for connecting the substrate electrodes of said ninth and tenth IG-FET's to said first terminal, means for connecting the substrate electrodes of said eleventh and twelfth IG-FET's to said reference voltage input terminal, and means for connecting the gate terminals of said thirteenth and fourteenth IG-FET's to said storage output terminal.

Claim 8

A level shifting circuit device according to claim 5, in which said storage circuit includes a storage output terminal, a fifth IG-FET of said other conductive channel type which is connected between said storage output terminal and said output terminal and the substrate electrode of which is connected to said first terminal, a sixth IG-FET of said other conductive channel type which is connected between said storage output terminal and said output terminal and the substrate electrode of which is grounded, and a capacitor connected between said storage output terminal and a ground, the gate electrode of said fifth IG-FET being supplied with a signal having a polarity opposite to that of said second pulse signal, the gate electrode of said sixth IG-FET being supplied with said second pulse signal; and which further comprises an inverter composed of seventh and eighth IG-FET's for inverting the polarity of an output from said storage circuit.

Claim 9

A level shifting circuit device according to claim 1, wherein said first conductive path includes said first IG-FET connected between said first terminal and said output terminal; said second conductive path includes a third IG-FET of said other conductive channel type connected in series to said second IG-FET and between said output terminal and said reference voltage input terminal; and said circuit arrangement includes means for applying a specified voltage to the gate electrode of said second IG-FET, means for applying said second pulse signal to the gate electrode of said third IG-FET, and means for applying said logic signal to said reference voltage input terminal.

Claim 10

A level shifting circuit device according to claim 1, wherein said first conductive path includes said first IG-FET connected between said first terminal and said output terminal; said second conductive path includes parallel-series logic circuit having a plurality of IG-FET's of said other conductive channel type connected in series between said output terminal and said reference voltage input terminal; and said circuit arrangement includes means for applying said second pulse signal to the gate electrode of said third IG-FET and means for applying first, second, third, fourth and fifth low amplitude logic signals VI VI 12, VI 21, VI 22 and VI 0 to the gate electrodes of said plurality of IG-FET's and both source electrodes of said fifth and seventh IG-FET's, respectively, there being established between said first to fifth logic signals VI 11, VI 12, VI 21, VI 22 and VI 0 and said logic signal VI a relation expressed by the logical formula: VI = VI 0 + VI 11 .sup.. VI 12 + VI 21 .sup.. VI 22.

Claim 11

A level shifting circuit device according to claim 8, which further comprises at least one of a storage circuit for storing an output signal from said level shifting circuit device and a stabilizer circuit for stabilizing in terms of logic level an output signal from said storage circuit.

Claim 12

A level shifting circuit device according to claim 10, wherein said storage circuit includes a storage output terminal, fifth and sixth IG-FET's of said one conductive channel type connected in series between said storage output terminal and said first terminal, and seventh and eighth IG-FET's of said other conductive channel type connected in series between said storage output terminal and said reference voltage input terminal, the gate electrodes of said sixth and seventh IG-FET's being connected to said output terminal, the gate electrode of said fifth IG-FET being supplied with a signal having a polarity opposite to that of said second pulse signal, the gate electrode of said eighth IG-FET being supplied with said second pulse signal; and said stabilizer circuit includes ninth and tenth IG-FET's of said one conductive channel type connected in series between said first terminal and said storage output terminal, eleventh and twelfth IG-FET's of said other conductive channel type connected in series between said storage output terminal and said reference voltage input terminal, means for connecting commonly the gate electrodes of said tenth and eleventh IG-FET's, a thirteenth IG-FET of said other conductive channel type connected between said commonly connecting point and said first terminal, a fourteenth IG-FET of said other conductive channel type connected between said commonly connecting point and said reference voltage input terminal, means for connecting the substrate electrodes of said ninth and tenth IG-FET's to said first terminal, means for connecting the substrate electrodes of said eleventh and twelfth IG-FET's to said reference voltage input terminal, and means for connecting the gate terminal of said thirteenth and fourteenth IG-FET's to said storage output terminal.

Claim 13

A level shifting circuit device according to claim 10, wherein said second IG-FET is connected in parallel further to a fourth IG-FET of said other conductive channel type, and the gate electrodes of said second and fourth IG-FET's and both source electrodes of said second and fourth IG-FET's are supplied with logic signals VI 2, VI 3 and VI 1, respectively, there being established between said logic signals VI 2, VI 3 and VI 1 and said logic signal VI a relation expressed by the logical formula: VI = VI 1 + VI 2 + VI 3; said storage circuit includes a storage output terminal, a second power source terminal having a voltage of E 2 volt, a third power source terminal having a voltage of E 3 volt, a fourth power source terminal having a voltage of E 4 volt, fifth and sixth IG-FET's of said one conductive channel type connected in series between said storage output terminal and said fourth power source, means for connecting the substrate electrodes of the fifth and sixth IG-FET's to said second or fourth power source terminal, the gate electrode of said fifth IG-FET being supplied with a signal having a pulse height of E 2 volt and subjected to inversion of substantially the same third pulse signal as said second pusle signal, seventh and eighth IG-FET's of said other conductive channel type connected in series between said storage output terminal and said third power source terminal, the gate electrode of said eighth IG-FET being supplied with said third pulse signal, means for connecting the substrate electrodes of said seventh and eighth IG-FET's to a ground or said third power source terminal, means for connecting the gate electrodes of said sixth and seventh IG-FET's to said output terminal of said level shifting circuit, and a capacitor connected between said storage output terminal and ground; and said stabilizer circuit includes ninth and tenth IG-FET's of said one conductive channel type connected in series between said fourth power source terminal and said storage output terminal, means for connecting the substrate electrodes of said ninth and tenth IG-FET's to said second or fourth power source terminal, the gate electrode of said ninth IG-FET being supplied with said third pulse signal, eleventh and twelfth IG-FET's of said other conductive channel type connected in series between said storage output terminal and said third power source terminal, means for connecting the substrate electrodes of said eleventh and twelfth IG-FET's to said ground or third power source terminal, the gate electrode of said twelfth IG-FET being supplied with said third puse signal, a thirteenth IG-FET of said one conductive channel type and a fourteenth IG-FET of said other conductive channel type connected in series between said fourth power source terminal and said third power source terminal, means for connecting the gate electrodes of said thirteenth and fourteenth IG-FET's to said storage output terminal, means for connecting the substrate electrode of said thirteenth IG-FET to said second or fourth power source terminal, means for connecting the substrate electrode of said fourteenth IG-FET to said ground or third power source terminal, and means for connecting the gate electrodes of said tenth and eleventh IG-FET's commonly to the drain electrodes of said thirteenth and fourteenth IG-FET's.

Claim 14

A level shifting circuit device according to claim 10, wherein said storage circuit includes an inverter circuit having a fourth IG-FET of said one conductive channel type and a fifth IG-FET of said other conductive channel type connected in series between said first terminal and a ground, a sixth IG-FET of said one conductive channel type and a seventh IG-FET of said other conductive channel type the source electrodes of which are individually supplied with an output from said inverter and the drain electrodes of which are connected to each other, and means for connecting the substrate electrodes of said sixth and seventh IG-FET's to said first terminal and said ground, respectively, the gate electrodes of said sixth and seventh IG-FET's being supplied with a signal subjected to inversion of said second pulse signal and said second pulse signal, respectively.

Claim 15

A level shifting circuit device according to claim 1, wherein said first conductive path includes said first IG-FET; said second conductive path includes said second IG-FET connected between said output terminal and said reference voltage input terminal; and said circuit arrangement includes means for applying said first pulse signal to the gate electrode of said first IG-FET, means for applying said low amplitude logic signal commonly to the gate electrodes of said second and third IG-FET's, and means for applying a signal subjected to inversion of said second pulse signal to the source electrode of said second IG-FET through said reference voltage input terminal.

Claim 16

A level shifting circuit device according to claim 1, wherein said first conductive path includes said first IG-FET; said second conductive path includes a plurality of IG-FET's of said other conductive channel type connected in series between said output terminal and said reference voltage terminal; and said circuit arrangement includes means for applying first, second, third and fourth logic signals VI 11, VI 12, VI 21 and VI 22 to the gate electrodes of said plurality of IG-FET's, respectively, there being established between said logic signals VI 11, VI 12, VI 21 and VI 22 and said logic signal VI a relation expressed by the logical formula: VI = VI 11 .sup.. VI 12 + VI 21 .sup.. VI 22, and means for applying a signal subjected to inversion of said second pulse signal to said reference voltage input terminal.

Claim 17

A level shifting circuit device according to claim 14, which further comprises at least one of a storage circuit for storing an output from said level shifting circuit device and a stabilizer circuit for stabilizing in terms of logic level an output signal from said storage circuit.

Claim 18

A level shifting circuit device according to claim 16, wherein said storage circuit includes a storage output terminal, fourth and fifth IG-FET's of said one conductive channel type connected in series between said storage output terminal and said first terminal and sixth and seventh IG-FET's of said other conductive channel type connected in series between said storage output terminal and said reference voltage input terminal, the gate electrodes of said fifth and sixth IG-FET's being connected to said output terminal, the gate electrode of said fourth IG-FET being supplied with said signal subjected to inversion of said second pulse signal, the gate electrode of said seventh IG-FET being supplied with said second pulse signal; and said stabilizer circuit includes eighth and ninth IG-FET's of said one conductive channel type connected in series between said first terminal and said storage output terminal, tenth and eleventh IG-FET's of said other conductive channel type connected in series between said storage output terminal and said reference voltage input terminal, means for connecting commonly the gate electrodes of said ninth and tenth IG-FET's, a twelfth IG-FET of said one conductive channel type connected between said commonly connecting point and said first terminal, a thirteenth IG-FET of said other conductive channel connected between said commonly connecting point and said reference voltage input terminal, means for connecting the substrate electrodes of said eighth and ninth IG-FET's to said first terminal, the substrate electrodes of said tenth and eleventh IG-FET's being connected to said reference voltage input terminal, and means for connecting the gate electrodes of said twelfth and thirteenth IG-FET's to said storage output terminal.

Claim 19

A level shifting circuit device according to claim 16, wherein said storage circuit includes an inverter circuit having a fourth IG-FET of said one conductive channel type and a fifth IG-FET of said other conductive channel type connected in series between said first terminal and a ground, a sixth IG-FET of said one conductive channel type and a seventh IG-FET of said other conductive channel type the source electrodes of which are supplied with an output from said inverter and the drain electrodes of which are connected to each other, means for connecting the substrate electrodes of said sixth and seventh IG-FET's to said first terminal and said ground, respectively, and a capacitor connected between a connecting point for connecting the drain electrodes of said sixth and seventh IG-FET's and said ground, the gate electrodes of said sixth and seventh IG-FET's being supplied with said signal subjected to inversion of said second pulse signal and said second pulse signal, respectively.

Claim 20

A level shifting circuit device according to claim 1, wherein said first conductive path includes said first IG-FET of said one conductive channel type connected between said first terminal and said output terminal; said second conductive path includes said second IG-FET of said other conductive channel type connected between said output terminal and said reference voltage input terminal; and said circuit arrangement includes an AND gate circuit whose output terminal is connected to the gate electrode of said second IG-FET, means for supplying said second pulse signal and said low amplitude logic signal to the input terminals of said AND circuit, and means for grounding said reference voltage input terminal.