Solid state resolver coordinate converter unit

Claim 2

Apparatus for performing digital coordinate transformation on n dimensional analog input data and ultimate outputting of the n dimensional data in a form compatible with analog utilization equipment comprising: a source of input vector and rotation angle data, and means for performing coordinate transformation on pairs of said input vector data through a given rotation angle while holding other of said input vector data constant and iterating in a like manner to perform coordinate transformation on different pairs of said input vector data.

Claim 3

The apparatus of claim 1 comprising: a separate means in said coordinate transformation means for temporarily storing the coordinate transformation data of each vector and rotation angle.

Claim 4

The apparatus of claim 2 comprising: means for the cross-addition of the outputs of pairs said temporary storage means.

Claim 5

The apparatus of claim 3 comprising: means for gating said temporary storage means to load binary zeroes after said data has been shifted.

Claim 6

The apparatus of claim 4 comprising: means for controlling the processing of said input data through said apparatus.

Claim 7

Apparatus for performing coordinate transformations on n dimensional analog input data comprising: a source of input vector and rotation angle data, means for performing digital coordinate transformation on pairs of said input vector data through a given rotation angle while holding other of said vector data constant and iterating in a like manner to perform coordinate transformation on different pairs of said input vector data, means for the digital cross addition of the results of transformation of said chosen pair of vector inputs, means for outputting the final coordinate transformation of said input vector and rotation angle, and means for controlling the processing of said input data through said apparatus.

Claim 8

Apparatus for performing coordinate transformations on n dimensional analog input data comprising: a source of input vector and rotation angle data, means for performing digital coordinate transformation on pairs of said input vector data through a given rotation angle while holding other of said vector data constant and iterating in a like manner to perform coordinate transformation on different pairs of said input vector data, means for the digital cross addition of the results of transformation of said chosen pair of vector inputs, means for outputting the final coordinate transformation of said input vector and rotation angle, and means for controlling the processing of said input data through said apparatus.

Claim 9

The apparatus according to claim 6 comprising: three sets of shift registers in said digital coordinate transformation means, each of said registers being dedicated to the computation of one of three orthogonal vectors and a fourth register being dedicated to provide rotation angle, whereby said control means may control digital conditions to said digital coordinate transformations means and select two of said three vector registers for cross-addition and said control means subsequently selects a different pair of vector registers to produce the coordinate transformation of said different set of registers.

Claim 10

The apparatus of claim 7 comprising: means for obtaining rotation angle comprising three sets of shift registers, two of which operate on digital tangent angle data to compute by cross addition rotation angle in the third register.

Claim 11

The apparatus of claim 8 comprising: means for gating said vector registers to accept the vector shifted one decimal each iteration 2 - .sup.(i -n ) X i by starting the shift of said registers from progressively increasing bits (LSB, LSB + 1, LSB + 2,...LSB + i) with each advance on i and means to load the shifted word with zeroes following the shift of the most significant register bit, by keying on the register's most significant bit prior to shift to determine if zero is logic 0 or logic 1, whereby the number of register bits is substantially minimized and program time is conserved.

Claim 12

The apparatus of claim 9 comprising: means for scale factor switching as a function of the weight of the total pointing vector and for range switching by increasing the signal gain of said means in discrete steps as the solution vector diminishes whereby the output scale integrity is maintained and solution sensitivity increased.

Claim 13

The apparatus according to claim 10 comprising: means for superposing a sawtooth signal upon said input vector and rotation angle data whereby truncation errors are eliminated.

Claim 14

A solid state system for performing digital coordinate transformation on three dimensional analog input data and ultimate analog outputting of the three dimensional data comprising: a multiplexer module for sampling at a predetermined rate a plurality of analog vector and angle data inputs, an analog-to-digital module operative upon signals from said multiplexer for encoding said analog signals and deriving binary data for subsequent digital computation, a tangent to angle converter module operative upon digital tangent θ from aid analog-to-digital converter for computing rotation angle θ, a digital computing resolver module operative upon signals from said analog-to-digital module and said tangent to angle converter for performing coordinate transformation on said signals from said analog-to-digital converter module and said tangent to angle converter, said digital computing resolver module comprising four shift registers, three of which are dedicated to the computation of three orthogonal vectors with the fourth register dedicated to the nulling of the rotation angle, said digital computing resolver module performing cross-addition on two of said orthogonal shift registers while holding the third of said orthogonal shift registers constant to produce coordinate transformation iterating in a like manner to arrive at the ultimate coordinate solution thereby eliminating storage means and intermediate registers, a digital-to-analog module for decoding signals from said digital computing resolver module and for compensating for growth factor of said signals during said computation, and a programmer module operable on the component modules of said apparatus for processing said signals through said apparatus on a programmed basis.

Claim 15

A solid state system for performing digital coordinate transformation on three dimensional analog input data and ultimate analog outputting of the three dimensional data comprising: a multiplexer module for sampling at a predetermined rate a plurality of analog vector and angle data inputs, an analog-to-digital module operative upon signals from said multiplexer for encoding said analog signals and deriving binary data for subsequent digital computation, a tangent to angle converter module operative upon digital tangent θ from aid analog-to-digital converter for computing rotation angle θ, a digital computing resolver module operative upon signals from said analog-to-digital module and said tangent to angle converter for performing coordinate transformation on said signals from said analog-to-digital converter module and said tangent to angle converter, said digital computing resolver module comprising four shift registers, three of which are dedicated to the computation of three orthogonal vectors with the fourth register dedicated to the nulling of the rotation angle, said digital computing resolver module performing cross-addition on two of said orthogonal shift registers while holding the third of said orthogonal shift registers constant to produce coordinate transformation iterating in a like manner to arrive at the ultimate coordinate solution thereby eliminating storage means and intermediate registers, a digital-to-analog module for decoding signals from said digital computing resolver module and for compensating for growth factor of said signals during said computation, and a programmer module operable on the component modules of said apparatus for processing said signals through said apparatus on a programmed basis.

Claim 16

A digital computer resolver comprising: three sets of shift registers, each of said registers being dedicated to the computation of one of three orthogonal vectors, and a fourth register being dedicated to provide rotation angle, said resolver selecting two of said three vector registers and said rotation angle register for cross-addition to produce coordinate transformation of a source of input vector and rotation data while holding the third vector register constant and thereafter selecting a different set of two vector registers and said rotation angle register for performing coordinate transformation on said different set of vector registers.

Claim 17

A digital computer resolver comprising: three sets of shift registers, each of said registers being dedicated to the computation of one of three orthogonal vectors, and a fourth register being dedicated to provide rotation angle, said resolver selecting two of said three vector registers and said rotation angle register for cross-addition to produce coordinate transformation of a source of input vector and rotation data while holding the third vector register constant and thereafter selecting a different set of two vector registers and said rotation angle register for performing coordinate transformation on said different set of vector registers.

Claim 18

The apparatus of claim 13 comprising: means for gating said vector registers to accept the vector shifted one decimal each iteration [2 - .sup.(i -n ) X i ] by starting the shift of said registers from progressively increasing bits (LSB, LSB+1, LSB+2,. . .LSB+i) with each advance on i, and means to load the shifted word with zeroes following the shift of the most significant register bit, by keying on the register's most significant bit prior to shift to determine if zero is logic 0 or logic 1, whereby the number of register bits is substantially minimized and program time is conserved.

Claim 19

A tangent to angle converter comprising: three sets of shift registers, two of said registers dedicated to operate on tangent angles from an analog to digital converter and to compute angle θ in the third register by cross adding of tangent data in said registers dedicated to operate on tangent angles, means for gating said tangent registers to accept the tangent data shifted one decimal each iteration [2 - .sup.(i -n ) X i ] by starting the shift of said registers from progressively increasing bits (LSB, LSB+1, LSB+2,. . .LSB+i) with each advance on i, and means to load the shifted word with zeros following the shift of the most significant register bit, by keying on the registers most significant bit prior to shift to determine if zero is logic 0 or logic 1, whereby the number of register bits is substantially minimized and program time is conserved.

Claim 20

A tangent to angle converter comprising: three sets of shift registers, two of said registers dedicated to operate on tangent angles from an analog to digital converter and to compute angle θ in the third register by cross adding of tangent data in said registers dedicated to operate on tangent angles, means for gating said tangent registers to accept the tangent data shifted one decimal each iteration [2 - .sup.(i -n ) X i ] by starting the shift of said registers from progressively increasing bits (LSB, LSB+1, LSB+2,. . .LSB+i) with each advance on i, and means to load the shifted word with zeros following the shift of the most significant register bit, by keying on the registers most significant bit prior to shift to determine if zero is logic 0 or logic 1, whereby the number of register bits is substantially minimized and program time is conserved.

Claim 23

The method of claim 16 including superposing a sawtooth signal upon said input vector and rotation angle data, thereby eliminating truncation errors.