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Method for reducing the defect density of an integrated circuit utilizing ion implantation

Assignee: Signetics Corp
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Filing: 1975-09-22
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Granted: 1976-08-24
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Expires: 1995-09-22
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Abstract

Abstract The buried layer of an integrated circuit is produced by use of a grated mask. The growth of silicon dioxide in the exposed areas of the grate forms a stepped surface. Thereafter ion implantation in these areas and then merging the implanted regions forms a single buried region having a corrugated surface on which an epitaxial layer is grown. Such corrugated surface reduces the defect regions in the epitaxial layer.

Inventors

  • 👤 Vittorio De Nora
  • 👤 Bohumil Polata

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 06:05
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/21; H10P30/212; H10W; H10W15/00; H10W15/01; Y; Y10; Y10S; Y10S148/00; Y10S148/003; Y10S148/037; Y10S148/039; Y10S148/085; Y10S148/097; Y10S148/145; Y10S438/00; Y10S438/938

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 160 words
In a method for reducing the defect density of an integrated circuit having a semiconductor substrate, a buried region and an epitaxial layer grown over said substrate and buried region, said epitaxial layer including a plurality of integrated devices occupying a predetermined extended area which is substantially coextensive with said buried region said method comprising the following steps: providing a semiconductor substrate having a surface; forming a grated mask on said surface having alternate elongated portions respectively covering and exposing said surface; forming a relatively thin, compared to said mask, protective layer; covering exposed portions of said surface by a thermal oxide growth technique in which a portion of said substrate is used up in the formation of the thin layer; ion-implanting conductivity determining impurities through said protective layers and into said semiconductor body to form a plurality of elongated regions; merging said elongated regions into a single region; and growing said epitaxial layer over said substrate and single region.
Claim 2
Dependent Claim 160 words
In a method for reducing the defect density of an integrated circuit having a semiconductor substrate, a buried region and an epitaxial layer grown over said substrate and buried region, said epitaxial layer including a plurality of integrated devices occupying a predetermined extended area which is substantially coextensive with said buried region said method comprising the following steps: providing a semiconductor substrate having a surface; forming a grated mask on said surface having alternate elongated portions respectively covering and exposing said surface; forming a relatively thin, compared to said mask, protective layer; covering exposed portions of said surface by a thermal oxide growth technique in which a portion of said substrate is used up in the formation of the thin layer; ion-implanting conductivity determining impurities through said protective layers and into said semiconductor body to form a plurality of elongated regions; merging said elongated regions into a single region; and growing said epitaxial layer over said substrate and single region.

References Cited (Backward Citations)

US3260902A Cited
US3283223A Cited
US3436282A Cited
US3510736A Cited
US3600241A Cited
US3717790A Cited
US3902926A Cited
US3916431A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-08-24 1980-02-23 1980-08-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-08-24 1984-02-23 1984-08-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-08-24 1988-02-23 1988-08-24 $7700.00 Window Closed / Lapsed

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