Gate assist turn-off, amplifying gate thyristor and a package assembly therefor

Claim 1

An amplifying gate thyristor with gate assist turn-off capability comprising: A. an amplifying gate thyristor disposed in a first semiconductor body having first and second major surfaces, said thyristor comprising (1 ) first, second, third and fourth impurity regions of alternate conductivity-type disposed through the body from said first major surface to said second major surface to form PN junctions between adjacent regions and main cathode-emitter, cathode-base, anode-base and anode-emitter regions, respectively; (2) fifth impurity region disposed in said semiconductor body adjoining said first major surface spaced adjacent said first impurity region to form a PN junction with said second impurity region and a pilot cathode-emitter region; (3) cathode and anode electrodes affixed to said first and second major surfaces, respectively, to make ohmic contact with the main cathode-emitter region and the anode-emitter region, respectively; (4) gate electrode affixed on said first major surface to make ohmic contact with the cathode-base region adjacent to and spaced from the pilot cathode-emitter region opposite from the main cathode-emitter region; and (5) floating electrode affixed on said first major surface spaced adjacent the gate and cathode electrodes to make ohmic contact with the pilot cathode-emitter region and the cathode-base region between the main and pilot cathode-emitter regions; B. an encapsulation means adapted for packaging said amplifying gate thyristor therein, said encapsulation means including a locator means for aligning and supporting a gate contact to make ohmic contact with said gate electrode of said thyristor, and adapted to support and align a diode relative to said gate electrode to make ohmic contact to said gate contact of the locator means and said floating electrode of said thyristor; and C. a diode disposed in a second semiconductor body and having cathode and anode impurity regions forming a PN junction therebetween and adjoining opposed major surfaces of said second semiconductor body, respectively, said diode affixed to said locator means in said encapsulation means in alignment with said gate contact, said cathode region thereof making ohmic contact with said gate contact of said encapsulation means, and said anode region thereof making ohmic contact with an anode electrode affixed on a major surface of said second semiconductor body and adapted to make ohmic contact with the floating electrode of said thyristor.