Patent US888725A successfully refreshed from Google Patents.
Patent US3975671A successfully refreshed from Google Patents.
US3975671A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Capacitive voltage converter employing CMOS switches
Assignee: Intel Corp
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Filing: 1975-02-24
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Granted: 1976-08-17
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Expires: 1995-02-24
Abstract
Abstract A CMOS circuit for approximately tripling battery voltage particularly adaptable for use with liquid crystal displays such as used in watches. P-wells of the CMOS circuit are coupled to active circuit nodes rather than to battery potentials. In the presently preferred embodiment a hybrid circuit with external capacitors is used to increase overall efficiency.
Inventors
- 👤 Peter A. Stoll
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:20
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; G; G04; G04G; G04G19/00; G04G19/02; G04G19/04
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
175 words
An MOS integrated circuit disposed on a substrate of a first conductivity type, for coupling a capacitance means to a source of potential such that said capacitance means may be charged from said source of potential, and for coupling said capacitance means to a connection means comprising: a first well of a second conductivity type disposed on said substrate; said well being coupled to said capacitance means; a first transistor disposed in said first well, said first transistor including a pair of regions of said first conductivity type, one of said regions coupled to said source of potential and the other of said regions coupled to said capacitance means; and, a second transistor, said second transistor including a pair or regions of said first conductivity type, one of said regions coupled to said capacitance means and the other region coupled to said connection means; whereby said capacitance means may be charged from said source of potential then coupled in series with said source of potential or other capacitance means to provide a higher output potential.
Claim 2
Dependent Claim
175 words
An MOS integrated circuit disposed on a substrate of a first conductivity type, for coupling a capacitance means to a source of potential such that said capacitance means may be charged from said source of potential, and for coupling said capacitance means to a connection means comprising: a first well of a second conductivity type disposed on said substrate; said well being coupled to said capacitance means; a first transistor disposed in said first well, said first transistor including a pair of regions of said first conductivity type, one of said regions coupled to said source of potential and the other of said regions coupled to said capacitance means; and, a second transistor, said second transistor including a pair or regions of said first conductivity type, one of said regions coupled to said capacitance means and the other region coupled to said connection means; whereby said capacitance means may be charged from said source of potential then coupled in series with said source of potential or other capacitance means to provide a higher output potential.
Claim 3
Dependent Claim
20 words
The circuit defined by claim 1 wherein said second transistor is disposed in a well of said second conductivity type.
Claim 4
Dependent Claim
13 words
The circuit defined by claim 2 wherein said first conductivity type is n-type.
Claim 5
Dependent Claim
330 words
A CMOS integrated circuit disposed on a substrate of a first conductivity type for charging a capacitor from a source of potential, and for coupling said capacitor in series with said source of potential to provide a higher potential than said source of potential, said source of potential including a first and second potential terminal and said capacitor including a first and second capacitor terminal, comprising: a first transistor disposed on said substrate, said first transistor including a pair of regions of a second conductivity type, one of said regions coupled to said first potential terminals and the other of said regions coupled to said first capacitor terminal; a first p-well, said first p-well coupled to said second potential terminal; a second transistor disposed in said first p-well said second transistor including a pair of regions of said first conductivity type, one of said regions coupled to said first capacitor terminal and the other of said regions coupled to said second potential terminal; a second p-well disposed in said substrate, said second p-well coupled to said second capacitor terminal; a third transistor disposed in said second p-well, said third transistor including a pair of regions of said first conductivity type, one of said regions coupled to said second potential terminal and the other of said regions coupled to said second capacitor terminal; a fourth transistor disposed on said substrate, said fourth transistor including a pair of regions of said first conductivity type, one of said regions coupled to said second capacitor terminal; a fifth transistor disposed on said substrate, said fifth transistor including a pair of regions of said second conductivity type, one of said regions coupled to said first potential terminal and the other of said regions providing a common terminal with said other region of said fourth transistor; whereby said capacitor may be charged from said source of potential and then coupled in series with said source of potential to provide a higher potential at said common terminal.
Claim 6
Dependent Claim
330 words
A CMOS integrated circuit disposed on a substrate of a first conductivity type for charging a capacitor from a source of potential, and for coupling said capacitor in series with said source of potential to provide a higher potential than said source of potential, said source of potential including a first and second potential terminal and said capacitor including a first and second capacitor terminal, comprising: a first transistor disposed on said substrate, said first transistor including a pair of regions of a second conductivity type, one of said regions coupled to said first potential terminals and the other of said regions coupled to said first capacitor terminal; a first p-well, said first p-well coupled to said second potential terminal; a second transistor disposed in said first p-well said second transistor including a pair of regions of said first conductivity type, one of said regions coupled to said first capacitor terminal and the other of said regions coupled to said second potential terminal; a second p-well disposed in said substrate, said second p-well coupled to said second capacitor terminal; a third transistor disposed in said second p-well, said third transistor including a pair of regions of said first conductivity type, one of said regions coupled to said second potential terminal and the other of said regions coupled to said second capacitor terminal; a fourth transistor disposed on said substrate, said fourth transistor including a pair of regions of said first conductivity type, one of said regions coupled to said second capacitor terminal; a fifth transistor disposed on said substrate, said fifth transistor including a pair of regions of said second conductivity type, one of said regions coupled to said first potential terminal and the other of said regions providing a common terminal with said other region of said fourth transistor; whereby said capacitor may be charged from said source of potential and then coupled in series with said source of potential to provide a higher potential at said common terminal.
Claim 7
Dependent Claim
15 words
The circuit defined by claim 4 wherein said fourth transistor is disposed within a p-well.
Claim 8
Dependent Claim
20 words
The circuit defined by claim 5 wherein said p-well of said fourth transistor is coupled to said second capacitor terminal.
Claim 9
Dependent Claim
13 words
The circuit defined by claim 4 wherein said first conductivity type is n-type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-17 | 1980-02-16 | 1980-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-17 | 1984-02-16 | 1984-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-17 | 1988-02-16 | 1988-08-17 | $7700.00 | Window Closed / Lapsed |