US3971998A
Expired / Lapsed
US
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Recursive detector-oscillator circuit
Assignee: AT&T Inc
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Filing: 1975-05-02
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Granted: 1976-07-27
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Expires: 1995-05-02
Abstract
Abstract Disclosed is a recursive circuit capable of serving as a signal detector or as a signal generator. The circuit comprises a shift register capable of storing multilevel signals, and a feedback network responsive to an input signal and to the output signals of selected stages of the shift register. In the feedback network, the output signals of the selected stages are each multiplied by prechosen integers, and then added with the input signal to form a sum signal which is applied to the first stage of the shift register. The sum signal is developed by nonmodulo addition, and the multiplying integers are prechosen to cause the characteristic function of the circuit to be a cyclotomic polynomial. Detection of the presence in the input signal of a signal having a chosen frequency is accomplished by the sum signal excluding a predetermined threshold level. Signal generation is accomplished by presetting the register to a nonzero state and allowing the output signal to develop in accordance with the characteristic function of the circuit.
Inventors
- 👤 Bhaskarpillai Gopinath
- 👤 Robert Paul Kurshan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:37
CPC Classifications
H; H04; H04W; H04W84/00; H03; H03B; H03B28/00; H03D; H03D1/00; H03D3/00; H03H; H03H17/00; H03H17/02; H03H17/0248; H03H17/028; H03H17/04; H04B; H04B1/00; H04B1/06
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
67 words
A signal detection circuit comprising: a shift register; means for multiplying the output signals of selected stages of said shift register by predetermined integers to cause the characteristic function of said circuit to be a cyclotomic polynomial; means for forming a non-modulo sum of an input signal and of said integer multiplied signals; and means for applying said sum to the first stage of said shift register.
Claim 2
Dependent Claim
67 words
A signal detection circuit comprising: a shift register; means for multiplying the output signals of selected stages of said shift register by predetermined integers to cause the characteristic function of said circuit to be a cyclotomic polynomial; means for forming a non-modulo sum of an input signal and of said integer multiplied signals; and means for applying said sum to the first stage of said shift register.
Claim 3
Dependent Claim
111 words
A circuit comprising: a shift register of k stages; means for forming product signals R i X n -i where X n -i is the output signals of the i t stage of said shift register at time n and R i is a predetermined multiplicative integer associated with the i th stage of said shift register, such that for a function variable λ, the function ##EQU24## is a cyclotomic polynomial; means for developing a signal U n ; means for adding said product signals with said signal U n to form a signal ##EQU25## and means for applying said X n signal to the first stage of said shift register.
Claim 4
Dependent Claim
111 words
A circuit comprising: a shift register of k stages; means for forming product signals R i X n -i where X n -i is the output signals of the i t stage of said shift register at time n and R i is a predetermined multiplicative integer associated with the i th stage of said shift register, such that for a function variable λ, the function ##EQU24## is a cyclotomic polynomial; means for developing a signal U n ; means for adding said product signals with said signal U n to form a signal ##EQU25## and means for applying said X n signal to the first stage of said shift register.
Claim 5
Dependent Claim
17 words
The circuit of claim 2 wherein said k equals 2 and said F(λ) equals λ 2 -λ+1.
Claim 6
Dependent Claim
19 words
The circuit of claim 2 wherein said k equals 4 and said F(λ) equals λ 4 -λ 2 +1.
Claim 7
Dependent Claim
19 words
The circuit of claim 2 wherein said k equals 6 and said F(λ) equals λ 6 -λ 3 +1.
Claim 8
Dependent Claim
25 words
The circuit of claim 2 wherein said k equals 8 and said F(λ) equals λ 8 +λ 7 -λ 5 -λ 4 -λ 3 +λ+1.
Claim 9
Dependent Claim
20 words
The circuit defined in claim 2 wherein said means for developing a signal U n is a unit pulse generator.
Claim 10
Dependent Claim
32 words
The circuit defined in claim 2 wherein said means for developing a signal U n develops a signal U n that is nonzero for a predetermined finite duration and is zero thereafter.
Claim 11
Dependent Claim
53 words
The circuit defined in claim 2, further comprising a transversal network connected to selected delay elements of said shift register for developing a signal ##EQU26## where X n -i is the output signal of the i.sup. th stage of said shift register at time n and the C i 's are preselected integers.
Claim 12
Dependent Claim
161 words
A circuit comprising: a shift register of k stages having at least one of said k stages at a nonzero initial condition; means for forming product signals R i X n -1 where X n -1 is the output signals of the i th stage of said shift register at time n and R i is a predetermined multiplicative integer associated with the i th stage of said shift register, such that for a function variable λ, the function ##EQU27## is a cyclotomic polynomial; means for adding said product signals with U n an input signal to form a signal ##EQU28## means for applying said X n signal to the first stage of said shift register; and a transversal network connected to selected stages of said shift register for developing a signal ##EQU29## where x n -i is the output signal of the i th stage of said shift register at time n and the C i 's are preselected integers.
Claim 13
Dependent Claim
161 words
A circuit comprising: a shift register of k stages having at least one of said k stages at a nonzero initial condition; means for forming product signals R i X n -1 where X n -1 is the output signals of the i th stage of said shift register at time n and R i is a predetermined multiplicative integer associated with the i th stage of said shift register, such that for a function variable λ, the function ##EQU27## is a cyclotomic polynomial; means for adding said product signals with U n an input signal to form a signal ##EQU28## means for applying said X n signal to the first stage of said shift register; and a transversal network connected to selected stages of said shift register for developing a signal ##EQU29## where x n -i is the output signal of the i th stage of said shift register at time n and the C i 's are preselected integers.
Claim 14
Dependent Claim
33 words
The apparatus of claim 10 wherein said C i 's are preselected multiplicative real constants such that said signal Y n possesses transmission zeroes at some of the roots of said cyclotomic polynomial.
Claim 15
Dependent Claim
18 words
The circuit defined in claim 11 wherein said C i 's are rounded off to a prechosen accuracy.
Claim 16
Dependent Claim
13 words
The circuit defined in claim 11 wherein said U n is hard clipped.
Claim 17
Dependent Claim
97 words
A signal generator developing a clocked signal having a desired frequency comprising: a shift register; means for multiplying the output signals of selected stages of said shift register by predetermined integers to cause the characteristic function of said circuit to be a cyclotomic polynomial; means for forming a non-modulo sum of said integer multiplied signals and an input signal sequence of fixed duration having transmission zeros at all the roots of said cyclotomic polynomial except at the roots corresponding to said desired frequency; and means for applying said sum to the first stage of said shift register.
Claim 18
Dependent Claim
97 words
A signal generator developing a clocked signal having a desired frequency comprising: a shift register; means for multiplying the output signals of selected stages of said shift register by predetermined integers to cause the characteristic function of said circuit to be a cyclotomic polynomial; means for forming a non-modulo sum of said integer multiplied signals and an input signal sequence of fixed duration having transmission zeros at all the roots of said cyclotomic polynomial except at the roots corresponding to said desired frequency; and means for applying said sum to the first stage of said shift register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-27 | 1980-01-26 | 1980-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-27 | 1984-01-26 | 1984-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-27 | 1988-01-26 | 1988-07-27 | $7700.00 | Window Closed / Lapsed |