Slaving calculator chips

Claim 2

In an electronic system implemented on semiconductor chips where it is desired to operate in synchronism more than one chip in the system where at least one element common to the operation of both or all chips is responsive to sequentially generated operating states, the combination which comprises: a master clock for applying clock pulses to the clock input terminals of said chips, means connected to selected operating state output terminals from both or all of said chips for inhibiting flow of clock signals to one of the chips so long as said selected operating states differ.

Claim 3

In an electronic system implemented on semiconductor chips where it is desired to operate in synchronism more than one chip in the system where at least one element common to the operation of both or all chips is responsive to sequentially generated operating states, the combination which comprises:

Claim 4

In an electronic system implemented on semiconductor chips where it is desired to operate in synchronism more than one chip in the system where at least one element common to the operation of both or all chips is responsive to sequentially generated operating states, the combination which comprises:

Claim 5

a master clock for applying clock pulses to the clock input terminal of one of said chips,

Claim 6

a master clock for applying clock pulses to the clock input terminal of one of said chips,

Claim 7

a control gate in the circuit leading from the clock to the clock input terminal of the other of said chips,

Claim 8

a control gate in the circuit leading from the clock to the clock input terminal of the other of said chips,

Claim 9

comparator means connected to selected operating state output terminals from both or all of said chips, and

Claim 10

comparator means connected to selected operating state output terminals from both or all of said chips, and

Claim 11

a connection from said comparator to said gate for inhibiting flow of clock signals to said other of said chips so long as the selected operating states differ.

Claim 12

a connection from said comparator to said gate for inhibiting flow of clock signals to said other of said chips so long as the selected operating states differ.

Claim 13

An electronic system implemented on semiconductor chips that synchronizes a plurality of slave chips to a selected state of a master chip, comprising: a. a system clock with clock connections leading to all of the chips to control the operation of said slave and master chips, b. means for comparing operating state of said master chip with the states of said slave chips, and c. means for inhibiting the clock signal to said slave chips until said comparing means indicates identity in operating states.

Claim 14

An electronic system implemented on semiconductor chips that synchronizes a plurality of slave chips to a selected state of a master chip, comprising: a. a system clock with clock connections leading to all of the chips to control the operation of said slave and master chips, b. means for comparing operating state of said master chip with the states of said slave chips, and c. means for inhibiting the clock signal to said slave chips until said comparing means indicates identity in operating states.

Claim 15

An electronic system implemented on semiconductor chips that synchronizes a plurality of slave chips to a selected state of a master chip, comprising: a. a system clock with clock connections leading to all of the chips to control the operation of said slave and master chips, b. means for comparing operating state of said master chip with the states of said slave chips, and c. means for inhibiting the clock signal to said slave chips until said comparing means indicates identity in operating states, and wherein d. said system clock is connected separately to said master and slave by way of parallel transistors, e. a control transistor connected in parallel to the transistor leading to said slave, f. a pair of series transistors connected to turn off said control transistor when said series transistors conduct, g. means to apply to one of said series transistors, a selected state signal from said master, h. means to apply to the other of said series transistors a selected state signal from said slave, and i. means to invert the signal from one of said master and said slave for transmission of the system clock signal to said slave when said selected state signals are the same.

Claim 16

An electronic system implemented on semiconductor chips that synchronizes a plurality of slave chips to a selected state of a master chip, comprising: a. a system clock with clock connections leading to all of the chips to control the operation of said slave and master chips, b. means for comparing operating state of said master chip with the states of said slave chips, and c. means for inhibiting the clock signal to said slave chips until said comparing means indicates identity in operating states, and wherein d. said system clock is connected separately to said master and slave by way of parallel transistors, e. a control transistor connected in parallel to the transistor leading to said slave, f. a pair of series transistors connected to turn off said control transistor when said series transistors conduct, g. means to apply to one of said series transistors, a selected state signal from said master, h. means to apply to the other of said series transistors a selected state signal from said slave, and i. means to invert the signal from one of said master and said slave for transmission of the system clock signal to said slave when said selected state signals are the same.

Claim 17

An electronic calculator system implemented on semiconductor chips that synchronizes timing within such chips, comprising: a. a plurality of calculator chips, b. a system clock generator having a connection leading to each of said chips for clock control of the operation thereof, c. means connected to the chips for comparing the timing of operating states within said chips, d. means for separately disabling the connections of the clock generator to all but a first of said chips until said comparing means indicates identical timing of operating states between said first of said chips and another one of said chips.

Claim 18

An electronic calculator system implemented on semiconductor chips that synchronizes timing within such chips, comprising: a. a plurality of calculator chips, b. a system clock generator having a connection leading to each of said chips for clock control of the operation thereof, c. means connected to the chips for comparing the timing of operating states within said chips, d. means for separately disabling the connections of the clock generator to all but a first of said chips until said comparing means indicates identical timing of operating states between said first of said chips and another one of said chips.

Claim 21

The method of claim 6 in which an inhibit state is applied to those chips not identical, and in which the inhibit state is removed when the state of a given chip corresponds with that of said first chip.