US3970943A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog-to-pulse integrating converter
Assignee: United States Department of the Air Force
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Filing: 1975-03-27
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Granted: 1976-07-20
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Expires: 1995-03-27
Abstract
Abstract An analog-to-pulse integrating converter uses dual slope integration to achieve DC voltage to pulse rate conversion. An input signal is integrated, the integrator output is level detected and the integrator reset, at the same time there is issued an output pulse. The output pulse rate is proportional to the level of the DC input signal.
Inventors
- 👤 Everett E. Chapman
- 👤 Thomas H. Crocker
- 👤 Barry N. Levitt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:59
CPC Classifications
H; H03; H03K; H03K7/00; H03K7/06
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
215 words
An analog-to-pulse integrating converter being comprised of analog means to integrate a bipolar DC signal, a feedback capacitor for said integrating means, an input resistor connected to said analog integrator means, said input resistor receiving said bipolar DC signal with said analog integrating means yielding as an output signal, the integral of the bipolar DC signal at a scale factor dependent on said input resistor and said feedback capacitor, said output signal also being positive or negative swinging, first and second level detector receiving the output signals from said analog integrating means, said first level detector being for positive levels and the second for negative levels, with said level detectors providing pulse output signals when said analog integrating means reaches a predetermined level, clock means to provide pulses at a predetermined frequency, first and second flip-flops receiving output pulses from said first and second level detectors, respectively, said first and second flip-flops also receiving the clock pulses to permit clocked synchronized first and second output pulses to be obtained from said first and second flip-flops, respectively, first and second positive and negative predetermined reference voltage sources normally disconnected, and switching means to connect said positive and negative reference voltage sources to said integrating means upon receiving said clocked synchronized first and second output pulses, respectively.
Claim 2
Dependent Claim
215 words
An analog-to-pulse integrating converter being comprised of analog means to integrate a bipolar DC signal, a feedback capacitor for said integrating means, an input resistor connected to said analog integrator means, said input resistor receiving said bipolar DC signal with said analog integrating means yielding as an output signal, the integral of the bipolar DC signal at a scale factor dependent on said input resistor and said feedback capacitor, said output signal also being positive or negative swinging, first and second level detector receiving the output signals from said analog integrating means, said first level detector being for positive levels and the second for negative levels, with said level detectors providing pulse output signals when said analog integrating means reaches a predetermined level, clock means to provide pulses at a predetermined frequency, first and second flip-flops receiving output pulses from said first and second level detectors, respectively, said first and second flip-flops also receiving the clock pulses to permit clocked synchronized first and second output pulses to be obtained from said first and second flip-flops, respectively, first and second positive and negative predetermined reference voltage sources normally disconnected, and switching means to connect said positive and negative reference voltage sources to said integrating means upon receiving said clocked synchronized first and second output pulses, respectively.
Claim 3
Dependent Claim
22 words
An analog-to-pulse integrating converter as described in claim 1 wherein said first and second level detectors consist of first and second comparators.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-20 | 1980-01-19 | 1980-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-20 | 1984-01-19 | 1984-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-20 | 1988-01-19 | 1988-07-20 | $7700.00 | Window Closed / Lapsed |