Bidirectional vco for a closed loop position measuring system

Claim 2

A bidirectional voltage controlled oscillator comprised of means for integrating a DC input signal to produce an integrator output signal with a polarity related to that of said input signal, means for determining when the amplitude of said integrator output signal exceeds predetermined positive and negative amplitude levels, means activated by said determining means for generating a single output pulse each time said predetermined level polarity, of either polarity, means for transmitting a signal representing the polarity of said integrator output signal at the time either of said predetermined levels has been exceeded, and means responsive to said pulse generating means for resetting said integrating means in response to each pulse generated.

Claim 3

A bidirectional voltage controlled oscillator as defined in claim 1 wherein said determining means is comprised of one pair of voltage comparators, one for transmitting a signal of a given level when said integrator output signal exceeds said predetermined level of one polarity and another for transmitting a signal of said given level when said integrator output signal exceeds said predetermined level of another polarity, and means coupling said signals transmitted by said pair of comparators to said pulse generating means for activating said pulse generating means immediately upon either of said comparators determining either of said predetermined levels has been exceeded.

Claim 4

A bidirectional voltage controlled oscillator as defined in claim 2 wherein said means for transmitting said signal representing the polarity of said integrator output signal at the time either of said predetermined levels has been exceeded is comprised of a binary storage element having a set and reset input terminals for placing said binary storage element in respective set and reset states, and means for connecting said set input terminal of said binary storage element to receive said signal transmitted by said one comparator, and means for connecting said reset input terminal of said binary storage element to receive said signal transmitted by said other comparator.

Claim 5

A bidirectional voltage controlled oscillator as defined in claim 1 wherein said pulse generating means is comprised of a binary storage element having a binary output terminal, and having an input terminal connected to be set by said determining means in response to determining when said integrator output signal exceeds either of said predetermined positive and negative elements, a source of clock pulses, counting means connected to said binary output terminal to be enabled by said binary storage means for counting clock pulses from said source, and means coupling said counting means to said binary storage means for resetting said binary storage means when a predetermined number of clock pulses have been counted.

Claim 6

A bidirectional voltage controlled oscillator as defined in claim 4, wherein said single output pulse, generated each time said predetermined level is actuated of either polarity, is derived from said binary output terminal of said binary storage element, including means connected to said binary output terminal of said binary storage element and said input terminal of said binary storage element for transmitting clock pulses from said source as additional output pulse of said generating means after said single output pulses has been generated when said means for resetting said integrating means fails to reset said integrating means in response to said single pulse generated, and to continue transmitting clock pulses from said source until said means for resetting said integrating means succeeds in resetting said integrating means.

Claim 7

In combination, an analog bipolar integrator responsive to a bipolar DC input signal for prodUcing a ramp output signal having a slope proportional to the amplitude of said DC input signal and a polarity corresponding to the polarity of said DC input, a pair of voltage comparators connected to receive said ramp signal, one comparator for determining when said ramp signal exceeds a predetermined threshold level of a given polarity and the other comparator for determining when said ramp signal exceeds a predetermined threshold level of a polarity opposite said given polarity, a pulse generating means coupled to said pair of comparators for producing a single output pulse each time said ramp signal crosses one of said threshold levels of either polarity from a level closer to zero, means responsive to said output pulse for resetting said integrator, thereby causing said integrator, pair of comparators and pulse generating means to operate in combination to produce a train of pulses at a rate proportional to the amplitude of said DC error signal, and a flip-flop having a first input terminal connected to said one comparator for setting said flip-flop to a given state when said ramp output signal exceeds said threshold level of said one polarity, and a second input terminal connected to said other comparator for setting said flip-flop to a state opposite said given state when said ramp signal exceeds said threshold level of said other polarity, thereby continually and correctly determining and storing polarity information of said DC input signal for use with said train of pulses.

Claim 8

In combination, an analog bipolar integrator responsive to a bipolar DC input signal for prodUcing a ramp output signal having a slope proportional to the amplitude of said DC input signal and a polarity corresponding to the polarity of said DC input, a pair of voltage comparators connected to receive said ramp signal, one comparator for determining when said ramp signal exceeds a predetermined threshold level of a given polarity and the other comparator for determining when said ramp signal exceeds a predetermined threshold level of a polarity opposite said given polarity, a pulse generating means coupled to said pair of comparators for producing a single output pulse each time said ramp signal crosses one of said threshold levels of either polarity from a level closer to zero, means responsive to said output pulse for resetting said integrator, thereby causing said integrator, pair of comparators and pulse generating means to operate in combination to produce a train of pulses at a rate proportional to the amplitude of said DC error signal, and a flip-flop having a first input terminal connected to said one comparator for setting said flip-flop to a given state when said ramp output signal exceeds said threshold level of said one polarity, and a second input terminal connected to said other comparator for setting said flip-flop to a state opposite said given state when said ramp signal exceeds said threshold level of said other polarity, thereby continually and correctly determining and storing polarity information of said DC input signal for use with said train of pulses.

Claim 9

The combination of claim 6 wherein said pulse generating means comprises a flip-flop so coupled to said pair of comparators as to be set to a given state each time said ramp signal crosses one of said threshold levels of either polarity from a level closer to zero, and means for resetting said pulse generating flip-flop after the lapse of a predetermined period of time.

Claim 10

The combination of claim 7 including a source of clock pulses operating at a rate greater than the maximum rate of output pulses which can be produced by said pulse generating means cooperating with said integrator and pair of comparators, a first logic gate connected to said pair of comparators and said pulse generating flip-flop to produce a control signal when said means for resetting said integrator has failed to reduce said ramp output signal below said threshold levels of said voltage comparators and generation of a single pulse has been terminated by said pulse generating flip-flop being reset, a second logic gate coupled to said first logic gate and to said clock pulse source for transmitting clock pulses in response to said control signal, and means for combining into said train of pulses produced by said pulse generating flip-flop all clock pulses transmitted by said second logic gate.

Claim 11

The combination of claim 8 wherein said means for resetting said pulse generating means comprises a counter connected to said pulse generating flip-flop for counting a predetermined number of said clock pulses, and a connection from said counter to said pulse generating flip-flop for resetting said pulse generating flip-flop upon said predetermined number of clock pulses being counted.

Claim 12

The combination of claim 9 wherein said predetermined number of clock pulses is two, and said counter includes means for resetting itself in response to a third pulse following the two pulses counted.