US3969744A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor devices
Assignee: US Philips Corp
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Filing: 1971-12-13
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Granted: 1976-07-13
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Expires: 1991-12-13
Abstract
Abstract A semiconductor device is described containing at least two insulating gate field effect transistors in a common wafer. One of the transistors exhibits high gain but the other transistor exhibits low gain as a result of selectively implanting into its channel neutral ions and crystal damage which reduce the effective mobility of charge carriers therein. In one embodiment, the low gain transistor serves as a load for the high gain transistor. In a second embodiment, the low gain transistor is a parasitic transistor formed between adjacent circuit elements.
Inventors
- 👤 Keith Harlow Nicholas
- 👤 Ronald Alfred Ford
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:49
CPC Classifications
H; H10; H10P; H10P95/00; H10D; H10D84/00; H10D84/80; H10D84/811; H10D84/817; H10D84/82; H10D84/83; H10D84/83125; H10D99/00; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/208; Y; Y10; Y10S; Y10S438/00; Y10S438/904
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
101 words
A semiconductor device comprising a common semiconductor wafer having a body portion of one type conductivity containing at least three spaced surface regions of the opposite type conductivity forming at least two field effect transistors each including a surface channel portion, and means for selectively reducing the gain of one of the field effect transistors, said gain reducing means comprising implanted neutral ions and associated semiconductor crystal lattice damage in the channel portion of said one transistor reducing the effective mobility of charge carriers therein in comparision with the mobility that would have existed in the absence of said implanted ions.
Claim 2
Dependent Claim
101 words
A semiconductor device comprising a common semiconductor wafer having a body portion of one type conductivity containing at least three spaced surface regions of the opposite type conductivity forming at least two field effect transistors each including a surface channel portion, and means for selectively reducing the gain of one of the field effect transistors, said gain reducing means comprising implanted neutral ions and associated semiconductor crystal lattice damage in the channel portion of said one transistor reducing the effective mobility of charge carriers therein in comparision with the mobility that would have existed in the absence of said implanted ions.
Claim 3
Dependent Claim
20 words
A device as claimed in claim 1 wherein the reduction of effective mobility is at least one order of magnitude.
Claim 4
Dependent Claim
32 words
A device as claimed in claim 1 wherein both field effect transistors have substantially the same dimensions, and the other field effect transistor has no implanted neutral ions in its channel portion.
Claim 5
Dependent Claim
35 words
A device as set forth in claim 3 wherein said one field effect transistor is electrically connected to the other field effect transistor to provide the circuit function of a load for the other transistor.
Claim 6
Dependent Claim
36 words
A device as set forth in claim 1 wherein the said one transistor includes a gate electrode on an insulator over the channel portion, and the implanted neutral ions have a peak concentration under the insulator.
Claim 7
Dependent Claim
31 words
A device as set forth in claim 1 wherein said one field effect transistor is a parasitic transistor, and its gain is reduced substantially to zero by the implanted neutral ions.
Claim 8
Dependent Claim
31 words
A device as set forth in claim 1 wherein the semiconductor is silicon, and the neutral ions are selected from the group consisting of an inert gas, nitrogen, tin and silicon.
Claim 9
Independent Claim
134 words
A method of making a semiconductor device comprising forming in a semiconductor body portion of one type conductivity at least three spaced surface regions of the opposite type conductivity defining at least two channel portions of field effect transistor capable when energized of exhibiting gain, masking the channel portion of one of the field effect transistors against neutral ion implantation, subjecting the body portion to neutral ion bombardment to selectively implant into the channel portion of the other transistor such a concentration of inert ions and associated semiconductor crystal lattice damage to reduce the gain of the associated transistor to a lower value by reducing the effective mobility of charge carriers in said channel portion, and thereafter processing the device so as to retain reduced gain of the other transistor in the final product.
Claim 10
Independent Claim
134 words
A method of making a semiconductor device comprising forming in a semiconductor body portion of one type conductivity at least three spaced surface regions of the opposite type conductivity defining at least two channel portions of field effect transistor capable when energized of exhibiting gain, masking the channel portion of one of the field effect transistors against neutral ion implantation, subjecting the body portion to neutral ion bombardment to selectively implant into the channel portion of the other transistor such a concentration of inert ions and associated semiconductor crystal lattice damage to reduce the gain of the associated transistor to a lower value by reducing the effective mobility of charge carriers in said channel portion, and thereafter processing the device so as to retain reduced gain of the other transistor in the final product.
Claim 11
Dependent Claim
22 words
A method as set forth in claim 8 wherein the subsequent processing includes heat treatments at a temperature of at most 500°C.
Claim 12
Dependent Claim
18 words
A method as set forth in claim 8 wherein the three surface regions are spaced equal distances apart.
Claim 13
Dependent Claim
93 words
A semiconductor device comprising a semiconductor wafer having a body portion containing at least two spaced surface regions forming at least one field effect transistor including a channel portion and a conductive gate electrode, and means for selectively reducing the gain of said one field effect transistor, said gain reducing means comprising implanted neutral ions and associated semiconductor crystal lattice damage in the channel portion of said one transistor reducing the effective mobility of charge carriers therein in comparison with the mobility that would have existed in the absence of said implanted ions.
Claim 14
Dependent Claim
93 words
A semiconductor device comprising a semiconductor wafer having a body portion containing at least two spaced surface regions forming at least one field effect transistor including a channel portion and a conductive gate electrode, and means for selectively reducing the gain of said one field effect transistor, said gain reducing means comprising implanted neutral ions and associated semiconductor crystal lattice damage in the channel portion of said one transistor reducing the effective mobility of charge carriers therein in comparison with the mobility that would have existed in the absence of said implanted ions.
Claim 15
Independent Claim
118 words
A method of making a semiconductor device comprising forming in a semiconductor body portion at least two spaced surface regions defining at least one channel portion of a field effect transistor having a conductive gate above the channel portion and capable when energized of exhibiting gain, subjecting the body portion to neutral ion bombardment to selectively implant into the channel portion of said transistor such a concentration of inert ions and associated semiconductor crystal lattice damage to reduce the gain of the associated transistor to a lower value by reducing the effective mobility of charge carriers in said channel portion, and thereafter processing the device so as to retain reduced gain of the transistor in the final product.
Claim 16
Independent Claim
118 words
A method of making a semiconductor device comprising forming in a semiconductor body portion at least two spaced surface regions defining at least one channel portion of a field effect transistor having a conductive gate above the channel portion and capable when energized of exhibiting gain, subjecting the body portion to neutral ion bombardment to selectively implant into the channel portion of said transistor such a concentration of inert ions and associated semiconductor crystal lattice damage to reduce the gain of the associated transistor to a lower value by reducing the effective mobility of charge carriers in said channel portion, and thereafter processing the device so as to retain reduced gain of the transistor in the final product.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-13 | 1980-01-12 | 1980-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-13 | 1984-01-12 | 1984-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-13 | 1988-01-12 | 1988-07-13 | $7700.00 | Window Closed / Lapsed |