Patent US3969587A successfully refreshed from Google Patents.
US3969587A
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US
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Selective transmission of prerecorded voice signals to subscribers of time-sharing telecommunication system
Assignee: Telecom Italia SpA
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Filing: 1975-07-14
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Granted: 1976-07-13
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Expires: 1995-07-14
Abstract
Abstract A dynamic memory UR containing n different message words, carried on as many endless signal tracks, works into a set of m temporal voice channels through a TDM switching matrix RC enabling any channel to be periodically connected, in its recurrent time slot, to a selected signal track. Messages synthesized from up to k words may provide information on the charge of a toll call, for example, as determined in a processor of a central office, the processor translating that information into data codes identifying corresponding signal tracks in response to a request from an inquiring subscriber. A first static memory M 1 , with m stages individually allocated to the several PCM channels, thereupon receives the data codes in respective sections of the stage associated with the inquiring subscriber and emits a start signal in the corresponding time slot informing a logic network LC of the presence of data stored therein, the logic network then monitoring selected outputs of the dynamic memory UR for the appearance of synchronizing signals prefacing their prerecorded message words. Coincidence of the first synchronizing signal with the start signal triggers the logic network LC into a sequence of operations in which a second static memory M 2 , connected in a loop circuit with that network, receives and re-emits bit combinations of progressively increasing numerical value identifying successive words of a message to be read out from the selected signal tracks to the inquiring subscriber. The readout of the message, ending after k words or upon the appearance of a terminal code from the processor entered in one or more sections of the allocated stage of memory M 1 , may be repeated at least once. A counter CO responsive to the start signal arrests the dynamic memory UR whenever no such signal appears within a scanning cycle of m time slots.
Inventors
- 👤 Piero Calcagno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:23
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407; G; G06; G06F; G06F3/00; G06F3/16; H04M; H04M3/00; H04M3/42; H04M3/487; H04M3/4872
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
355 words
In a time-division-multiplex telecommunication system with m temporal voice channels extending between respective subscriber stations and a central office, timing means at said central office for sequentially scanning said channels in a recurrent cycle of m time slots, and a processor at said central office responsive to selection signals from any subscriber station for emitting relevant call information, the combination therewith of: a dynamic memory provided with n endless signal tracks containing respective prerecorded audibly reproducible message words representing different types of call information available from said processor, each message word being prefaced on its track by a synchronizing signal, said dynamic memory having n first outputs emitting the message words and n second outputs emitting the synchronizing signals of respective tracks; first storage means provide with m principal memory stages respectively allocated to said m channels; asynchronously operative circuitry for loading a first memory stage, allocated to a channel serving an inquiring subscriber, with at least one data code received from said processor and identifying a signal track carrying relevant call information; synchronously operative circuitry controlled by said timing means and selectively connectable to any of said second outputs in response to a registered data code for initiating, upon the occurrence of a corresponding synchronizing signal, a periodic readout in recurrent time slots, assigned to the channel serving the inquiring subscriber, of a data code loaded into a principal memory stage allocated to the same channel; switch means responsive to said timing means for periodically connecting any one of said channels, during an assigned time slot, through a respective first output of said dynamic memory to a selected signal track thereof identified by a data code read out from a principal memory stage allocated to the respective channel, thereby transmitting the prerecorded message word of the selected signal track to the inquiring subscriber; and second storage means in said synchronously operative circuitry provided with m ancillary memory stages for respectively monitoring the activities of said m principal memory stages and terminating the readout of a data code therefrom after a period sufficient to transmit the entire prerecorded message word of the selected signal track.
Claim 2
Dependent Claim
355 words
In a time-division-multiplex telecommunication system with m temporal voice channels extending between respective subscriber stations and a central office, timing means at said central office for sequentially scanning said channels in a recurrent cycle of m time slots, and a processor at said central office responsive to selection signals from any subscriber station for emitting relevant call information, the combination therewith of: a dynamic memory provided with n endless signal tracks containing respective prerecorded audibly reproducible message words representing different types of call information available from said processor, each message word being prefaced on its track by a synchronizing signal, said dynamic memory having n first outputs emitting the message words and n second outputs emitting the synchronizing signals of respective tracks; first storage means provide with m principal memory stages respectively allocated to said m channels; asynchronously operative circuitry for loading a first memory stage, allocated to a channel serving an inquiring subscriber, with at least one data code received from said processor and identifying a signal track carrying relevant call information; synchronously operative circuitry controlled by said timing means and selectively connectable to any of said second outputs in response to a registered data code for initiating, upon the occurrence of a corresponding synchronizing signal, a periodic readout in recurrent time slots, assigned to the channel serving the inquiring subscriber, of a data code loaded into a principal memory stage allocated to the same channel; switch means responsive to said timing means for periodically connecting any one of said channels, during an assigned time slot, through a respective first output of said dynamic memory to a selected signal track thereof identified by a data code read out from a principal memory stage allocated to the respective channel, thereby transmitting the prerecorded message word of the selected signal track to the inquiring subscriber; and second storage means in said synchronously operative circuitry provided with m ancillary memory stages for respectively monitoring the activities of said m principal memory stages and terminating the readout of a data code therefrom after a period sufficient to transmit the entire prerecorded message word of the selected signal track.
Claim 3
Dependent Claim
44 words
The combination defined in claim 1 wherein said synchronously operative circuitry further includes a logic network connected in a closed loop with said second storage means for modifying the contents of said ancillary memory stages in response to a recurrence of said synchronizing signal.
Claim 4
Dependent Claim
118 words
The combination defined in claim 2 wherein each of said principal memory stages includes k sections for the storage of as many data codes simultaneously received from said processor in response to a selection from an inquiring subscriber, said synchronously operative circuitry comprising multiplexing means controlled by the contents of said ancillary memory stages in response to successive recurrences of said synchronizing signal for sequentially connecting said switch means to different sections of a loaded principal memory stage, said logic network being adapted to introduce a termination code into an ancillary memory stage in response to the recurrence of a synchronizing signal following the readout of data codes from all k sections of the corresponding principal memory stage.
Claim 5
Dependent Claim
48 words
The combination defined in claim 3, further comprising an end-of-message detector connected to said first storage means and working into said logic network for generating said termination code also in response to a special bit combination registered by said processor in a section of a principal memory stage.
Claim 6
Dependent Claim
86 words
The combination defined in claim 3 wherein said multiplexing means is provided with a first input connected to said second storage means and with a second input connected to said logic network, said second input being energizable with an overriding resetting signal from said logic network upon a second appearance of a synchronizing signal in any of said second outputs for temporarily deactivating said switch means during changeover from one signal track to another in the readout of data codes from a given principal memory stage.
Claim 7
Dependent Claim
46 words
The combination defined in claim 2 wherein said closed loop has a branch including a repetition controller responsive to a predetermined combination of bits from said second storage means and from said logic network for iteratively reading out the contents of a loaded principal memory stage.
Claim 8
Dependent Claim
80 words
The combination defined in claim 2, further comprising switchover means controlled by said timing means for establishing in each time slot a first period enabling said first storage means to be addressed via said synchronously operative circuitry, for the readout of a data code from any loaded principal memory stage, and a second period enabling said first storage means to be addressed via said asynchronously operative circuitry, to select an unloaded principal memory stage for loading with a data code.
Claim 9
Dependent Claim
41 words
The combination defined in claim 7, further comprising bistable means responsive to a stop signal from said logic network for generating in said asynchronous circuitry a clearing signal, effective in said second period, for unloading a heretofore loaded principal memory stage.
Claim 10
Dependent Claim
61 words
The combination defined in claim 1, further comprising a driving circuit for the activation of said dynamic memory, said driving circuit including counting means connected to said first storage means for ascertaining the presence of a data code in at least one of said m principal memory stages during a scanning cycle and deactivating said dynamic memory in the absence thereof.
Claim 11
Dependent Claim
37 words
The combination defined in claim 1 wherein said dynamic memory is provided with filter means connected to said first outputs for separating said synchronizing signal from said message words, said second outputs originating at said filter means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-13 | 1980-01-12 | 1980-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-13 | 1984-01-12 | 1984-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-13 | 1988-01-12 | 1988-07-13 | $7700.00 | Window Closed / Lapsed |