← Back to Patent Explorer
US3968453A Expired / Lapsed US ⏱️ 0.0 years remaining

Gain control circuit

Assignee: Sony Corp
•
Filing: 1974-12-02
•
Granted: 1976-07-06
•
Expires: 1994-12-02
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A signal to be controlled is applied to the base of an emitter-follower input transistor, the emitter of which is connected to an input terminal of a differential amplifier. This input terminal of the amplifier is connected by a diode to a controllable current source so that the base current of the differential amplifier input transistor is controlled. A constant current source is connected to the common emitter circuit of the differential amplifier, and the gain of the circuit is determined by the ratio of current in the latter source to current in the controllable source. A current conducting circuit, such as, an emitter load resistor, is connected to the emitter of the input transistor to hold the output impedance thereof at a substantially constant low value inspite of changes in the current of the controllable current source, Maximum gain of the circuit may be determined by separating the controllable current source into a controllable portion and a fixed portion in parallel so that the minimum current is at least as great as the current of the fixed portion. This limits the maximum circuit gain by limiting the maximum ratio of fixed current to controllable current. A fixed voltage source connected to the common circuit point between the controllable current source and the diode assures that the gain of the circuit will not fall below a selected minimum value.

Inventors

  • 👤 Masayuki Hongu
  • 👤 Tsutomu Niimura

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 17:35
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0035; H03G1/0052; H03G3/00; H03G3/02

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 229 words
A gain control circuit comprising: a differential amplifier including first and second differentially connected transistors, a base input circuit connected to the base of at least said first transistor and an output circuit; an input transistor; an impedance connecting the emitter of said input transistor to the base input circuit of the differential amplifier; an input signal voltage source connected to the base of said input transistor; a constant current source connected in series with the collector-emitter paths of said first and second differentially connected transistors between a power supply source and ground; a controllable current source; variable impedance means connecting said controllable current source to said base input circuit of said differential amplifier, the impedance value of said variable impedance means being controlled as a function of the current of said controllable current source so that the gain of said differential amplifier is determined by the ratio of the current of said constant current source to said current of the controllable current source; and current conducting circuit means connected to said emitter of said input transistor to carry part of the emitter current of said input transistor and thereby maintain a substantially low output impedance of said input transistor, as measured at said emitter thereof, even when said current of the controllable current source is reduced to a substantially small value for maximum gain of said differential amplifier.
Claim 2
Dependent Claim 229 words
A gain control circuit comprising: a differential amplifier including first and second differentially connected transistors, a base input circuit connected to the base of at least said first transistor and an output circuit; an input transistor; an impedance connecting the emitter of said input transistor to the base input circuit of the differential amplifier; an input signal voltage source connected to the base of said input transistor; a constant current source connected in series with the collector-emitter paths of said first and second differentially connected transistors between a power supply source and ground; a controllable current source; variable impedance means connecting said controllable current source to said base input circuit of said differential amplifier, the impedance value of said variable impedance means being controlled as a function of the current of said controllable current source so that the gain of said differential amplifier is determined by the ratio of the current of said constant current source to said current of the controllable current source; and current conducting circuit means connected to said emitter of said input transistor to carry part of the emitter current of said input transistor and thereby maintain a substantially low output impedance of said input transistor, as measured at said emitter thereof, even when said current of the controllable current source is reduced to a substantially small value for maximum gain of said differential amplifier.
Claim 3
Dependent Claim 62 words
The gain control circuit of claim 1 in which said controllable current source comprises a first section producing a variable current and a second section connected in parallel with said first section and producing a substantially constant current, whereby the minimum current of said controllable current source is not less than the value of said substantially constant current of said second section.
Claim 4
Dependent Claim 46 words
The gain control circuit according to claim 1 comprising, in addition, a substantially fixed voltage source connected between said controllable current source and said variable impedance means to limit the current of said controllable current source and thereby determine the minimum gain of the differential amplifier.
Claim 5
Dependent Claim 34 words
The gain control circuit according to claim 1 comprising detecting means connecting said controllable current source to said output circuit, whereby said controllable current source is controlled by the signal from said output circuit.

References Cited (Backward Citations)

US2878380A Cited
US3764931A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-07-06 1980-01-05 1980-07-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-07-06 1984-01-05 1984-07-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-07-06 1988-01-05 1988-07-06 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag