Methods of manufacturing multilayer interconnections for integrated circuits and to integrated circuits utilizing said method

Claim 1

Process of manufacturing multilayer interconnection patterns for interconnecting elements integrated over the same substrate comprising the steps of: a. forming a contact zone for each element; b. depositing over said substrate a first conductive layer of a first metal, etching according to a predetermined pattern, said first layer interconnecting some of said contact zones; c. depositing over said conductive layer a second layer of a metal easily oxidizable by a well defined thermal treatment and that upon oxidation forms an oxide having a high resistance to chemical agents and high dielectric properties; d. depositing protecting studs over said second layer, said studs extending over some of said contact zones and being made of a body resistant to said thermal treatment; e. treating the whole assembly thermally in an oxidizing atmosphere at elevated temperature, whereby the non-protected zones of said second layer are preferentially oxidized to a non-conductive oxide and thereby forming a third dielectric layer, and the non-protected zones of said second layer are at most only partially oxidized; f. depositing over said assembly a third conductive layer of said resistive metal as in step (b); and g. etching said third layer according to a predetermined pattern thereby interconnecting some of said contact zones.