Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
231 words
In a real-time computer, which, while in operation, performs the relocation of data in a memory from a first to a second memory field wherein the memory has means activated by a write pulse for writing data into a memory position defined by received address information, apparatus for writing identical data, stored in a data register, into both of said first and second memory fields during said relocation, said apparatus comprising: a first address register for storing a primary address belonging to said first memory field; a second address register for storing the address separation between said first and second memory fields; and a control circuit comprising an adder means provided with a first input connected to said first address register and a second input connected to said second address register, said adder means having means for producing a result address by adding said address separation to said primary address, a gate device having a first input for receiving said result address, a second input connected to said first address register and an output connected to said memory, a recording means for storing a relocation indication, and control means for controlling the transfer in a determined order of said primary address and said result address from said gate device to said memory, said control means including means for supplying to the memory an additional write pulse when said indication is present.
Claim 2
Dependent Claim
231 words
In a real-time computer, which, while in operation, performs the relocation of data in a memory from a first to a second memory field wherein the memory has means activated by a write pulse for writing data into a memory position defined by received address information, apparatus for writing identical data, stored in a data register, into both of said first and second memory fields during said relocation, said apparatus comprising: a first address register for storing a primary address belonging to said first memory field; a second address register for storing the address separation between said first and second memory fields; and a control circuit comprising an adder means provided with a first input connected to said first address register and a second input connected to said second address register, said adder means having means for producing a result address by adding said address separation to said primary address, a gate device having a first input for receiving said result address, a second input connected to said first address register and an output connected to said memory, a recording means for storing a relocation indication, and control means for controlling the transfer in a determined order of said primary address and said result address from said gate device to said memory, said control means including means for supplying to the memory an additional write pulse when said indication is present.
Claim 3
Dependent Claim
22 words
Arrangement in accordance with claim 1 wherein said determined order is such that said result address is obtained after said primary address.
Claim 4
Dependent Claim
22 words
Arrangement in accordance with claim 1 wherein said determined order is such that said result address is obtained before said primary address.