US3966515A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing high voltage field-effect transistors
Assignee: Teledyne Inc
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Filing: 1974-05-17
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Granted: 1976-06-29
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Expires: 1994-05-17
Abstract
Abstract A method of manufacturing field-effect transistors is disclosed which includes the steps of growing an epitaxial layer on a substrate wafer, forming channels of the desired conductivity on the wafer, forming the gate electrodes on the wafer and then forming source and drain electrodes on the wafer. The gate electrodes are formed by first masking the gate electrode area and performing a first boron deposition and boron diffusion step. A second boron deposition and diffusion step is then provided to enable the resultant field-effect transistor to operate at higher voltages.
Inventors
- 👤 Samuel Josepheus Guthrie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:17
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/17; H10P32/171; H10D; H10D30/00; H10D30/80; H10D30/83; H10P32/14; H10P32/1404
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
101 words
The method of manufacturing high voltage field-effect transistors, comprising the steps of: growing an epitaxial layer of a desired conductivity upon a substrate of the opposite conductivity, forming channels of desired conductivity on the wafer, forming gate regions on the wafer by the steps of: masking the wafer to expose only the gate region areas, forming a first boron deposition on the wafer, diffusing the first boron deposition into the wafer, forming a second boron deposition on the wafer, diffusing the second boron deposition into the wafer, and oxidizing the wafer, and forming the source and drain electrodes on the wafer.
Claim 2
Independent Claim
101 words
The method of manufacturing high voltage field-effect transistors, comprising the steps of: growing an epitaxial layer of a desired conductivity upon a substrate of the opposite conductivity, forming channels of desired conductivity on the wafer, forming gate regions on the wafer by the steps of: masking the wafer to expose only the gate region areas, forming a first boron deposition on the wafer, diffusing the first boron deposition into the wafer, forming a second boron deposition on the wafer, diffusing the second boron deposition into the wafer, and oxidizing the wafer, and forming the source and drain electrodes on the wafer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-29 | 1979-12-29 | 1980-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-29 | 1983-12-29 | 1984-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-29 | 1987-12-29 | 1988-06-29 | $7700.00 | Window Closed / Lapsed |