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US3965343A
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Modular system for performing the discrete fourier transform via the chirp-Z transform
Assignee: United States Department of the Navy
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Filing: 1975-03-03
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Granted: 1976-06-22
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Expires: 1995-03-03
Abstract
Abstract Two kinds of apparatus for combining N 2 chirp-Z transform (CZT) modu of length N 1 to perform a discrete Fourier transform (DFT) of length N 1 N 2 . The first method uses an auxiliary parallel-input, parallel-output, DFT device of size N 2 and allows the transform of size N 1 N 2 to be performed in the same time as is required for a single CZT module to perform a size N 1 transform. The second method uses an auxiliary parallel-input, serial-output, DFT device of size N 2 . If the second method is implemented entirely in a single technology, such as with charge-coupled devices (CCDs), it performs the size N 1 N 2 transform in N 2 times the amount of time required for a single CZT module to perform a size N 1 transform. If N 2 is a composite number, say N 2 = M 1 M 2 , the second method also permits the same hardware to perform M 1 simultaneous transforms of length N 1 M 2 .
Inventors
- 👤 Jeffrey M. Speiser
- 👤 Harper John Whitehouse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:57
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/19; G06G7/1921
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
158 words
Apparatus for combining N 2 ≦32 chirp-Z transform (CZT) modules of length N1≦256 in order to generate a discrete Fourier transform (DFT) of length N 1 N 2 comprising: a serial-to-parallel multiplexer to which may be applied a serial input signal and which has N 2 parallel outputs; a plurality of N 2 chirp-Z transform devices, each of whose inputs comprise the outputs of the serial-to-parallel multiplexer, the input signals being transformed into chirp-Z transform signals; a plurality of N 2 -1 multipliers, each one having an input connected to the output of the chirp-Z transform devices, the outputs comprising chirp-Z transformed signals, each signal having a different delay; and a parallel discrete Fourier transform (DFT) device of size N 2 , having as inputs the outputs of the N 2 -1 multipliers in addition to an output directly from one of the chirp-Z transform devices, its parallel outputs comprising the discrete Fourier transformed signals in parallel form.
Claim 2
Dependent Claim
158 words
Apparatus for combining N 2 ≦32 chirp-Z transform (CZT) modules of length N1≦256 in order to generate a discrete Fourier transform (DFT) of length N 1 N 2 comprising: a serial-to-parallel multiplexer to which may be applied a serial input signal and which has N 2 parallel outputs; a plurality of N 2 chirp-Z transform devices, each of whose inputs comprise the outputs of the serial-to-parallel multiplexer, the input signals being transformed into chirp-Z transform signals; a plurality of N 2 -1 multipliers, each one having an input connected to the output of the chirp-Z transform devices, the outputs comprising chirp-Z transformed signals, each signal having a different delay; and a parallel discrete Fourier transform (DFT) device of size N 2 , having as inputs the outputs of the N 2 -1 multipliers in addition to an output directly from one of the chirp-Z transform devices, its parallel outputs comprising the discrete Fourier transformed signals in parallel form.
Claim 3
Dependent Claim
132 words
The apparatus according to claim 1 wherein the serial-to-parallel multiplexer comprises: a recirculating binary shift register having N 2 cells, that is, of length N 2 ; a plurality of switching means, each of the switching means having as an input the signal which is to be chirp-Z transformed, the state of each of the switching means, that is, whether it permits the input signal to propagate through the switching means or not, is controllable by each of the cells of the shift register, a zero in a cell not permitting the input signal to propagate through the switching means, a 1 in the cell permitting the switching means to propagate a signal through the switching means, the parallel outputs of the multiplexer corresponding to the binary states of the shift register.
Claim 4
Dependent Claim
160 words
Apparatus for combining N 2 chirp-Z transform (CZT) modules of length N 1 in order to generate a discrete Fourier transform (DFT) of length N 1 N 2 , comprising: a serial-to-parallel multiplexer to which may be applied a serial input signal and which has N 2 parallel outputs: a plurality of N 2 chirp-Z transform devices, each of whose inputs comprise the outputs of the serial-to-parallel multiplexer, the input signals being transformed into chirp-Z transform signals: a plurality of N 2 -1 multipliers, each one having an input connected to the output of the chirp-Z transform devices, the outputs comprising chirp-Z transform signals, each signal having a different delay; and a parallel-input, serial-output, discrete Fourier transform (DFT) device of size N 2 , whose inputs comprise N 2 -1 outputs from the multipliers and another, direct, output from one of the chirp-Z transform devices, the output of the DFT device comprising the discrete Fourier transformed signals in serial form.
Claim 5
Dependent Claim
160 words
Apparatus for combining N 2 chirp-Z transform (CZT) modules of length N 1 in order to generate a discrete Fourier transform (DFT) of length N 1 N 2 , comprising: a serial-to-parallel multiplexer to which may be applied a serial input signal and which has N 2 parallel outputs: a plurality of N 2 chirp-Z transform devices, each of whose inputs comprise the outputs of the serial-to-parallel multiplexer, the input signals being transformed into chirp-Z transform signals: a plurality of N 2 -1 multipliers, each one having an input connected to the output of the chirp-Z transform devices, the outputs comprising chirp-Z transform signals, each signal having a different delay; and a parallel-input, serial-output, discrete Fourier transform (DFT) device of size N 2 , whose inputs comprise N 2 -1 outputs from the multipliers and another, direct, output from one of the chirp-Z transform devices, the output of the DFT device comprising the discrete Fourier transformed signals in serial form.
Claim 6
Dependent Claim
132 words
The apparatus according to claim 3, wherein the serial-to-parallel multiplexer comprises: a recirculating binary shift register having N 2 cells, that is, of length N 2 ; a plurality of switching means, each of the switching means having as an input the signal which is to be chirp-Z transformed, the state of each of the switching means, that is, whether it permits the input signal to propagate through the switching means or not, is controllable by each of the cells of the shift register, a zero in a cell not permitting the input signal to propagate through the switching means, a 1 in the cell permitting the switching means to propagate a signal through the switching means, the parallel outputs of the multiplexer corresponding to the binary states of the shift register.
Claim 7
Dependent Claim
184 words
A combination useful in apparatus for the generation of a discrete Fourier transform (DFT) comprising: a first delay line to which is applied a chirp signal, e i .sup.π(k -M ).spsp.2/2M, k = 0, 1, . . . , 2M-1, M > 1, the delay line having M output taps; a plurality of M multipliers, to which are applied parallel input signals, namely h 0 , h 1 , . . . h M -1 , the outputs from the taps of the first delay line also forming an input to each multiplier; a second delay line having M taps, to which is applied a chirp signal, e - i .sup.πk.spsp.2/2M, k =0, 1, . . . , 2M-1, the outputs of the taps of this delay line also forming inputs to the multipliers; and a signal summer, whose M inputs comprise the outputs of the multipliers, the summer having an output signal which is in the form of a discrete Fourier transform in serial form on the input signal, h 0 , h 1 , . . . , h M -1 .
Claim 8
Dependent Claim
184 words
A combination useful in apparatus for the generation of a discrete Fourier transform (DFT) comprising: a first delay line to which is applied a chirp signal, e i .sup.π(k -M ).spsp.2/2M, k = 0, 1, . . . , 2M-1, M > 1, the delay line having M output taps; a plurality of M multipliers, to which are applied parallel input signals, namely h 0 , h 1 , . . . h M -1 , the outputs from the taps of the first delay line also forming an input to each multiplier; a second delay line having M taps, to which is applied a chirp signal, e - i .sup.πk.spsp.2/2M, k =0, 1, . . . , 2M-1, the outputs of the taps of this delay line also forming inputs to the multipliers; and a signal summer, whose M inputs comprise the outputs of the multipliers, the summer having an output signal which is in the form of a discrete Fourier transform in serial form on the input signal, h 0 , h 1 , . . . , h M -1 .
Claim 9
Dependent Claim
55 words
The combination according to claim 5, further comprising: means for generating the chirp signal e i .sup.π(k-M).spsp.2/2M, k = 0, 1, . . . , 2M-1, and means for generating the chirp signal e + .sup.π k .spsp.2/2M, k having the same range; the combination comprising apparatus for the generation of the discrete Fourier transform.
References Cited (Backward Citations)
US3584782A
Cited
US3816729A
Cited
US3704826A
Cited
US3778604A
Cited
US3721812A
Cited
US3783258A
Cited
US3808412A
Cited
US3851162A
Cited
US3881097A
Cited
US3900721A
Cited
US3925648A
Cited
US3920974A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-22 | 1979-12-22 | 1980-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-22 | 1983-12-22 | 1984-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-22 | 1987-12-22 | 1988-06-22 | $7700.00 | Window Closed / Lapsed |