US3963942A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor charge transfer devices with dark current background cancellation
Assignee: AT&T Inc
•
Filing: 1975-03-06
•
Granted: 1976-06-15
•
Expires: 1995-03-06
Abstract
Abstract In order to reduce the steady dark current background effect on the output sequence of charge packets in a semiconductor charge transfer device, each charge packet on its first arrival at the output end of a transfer path is inverted with respect to a suitable reference level; and the inverted charge packet is then recirculated through the same transfer path for subsequent detection on its next arrival at the output end of the path.
Inventors
- 👤 Carlo Heinrich Sequin
- 👤 Peter Van Dyke Wilde
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:15
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/891; G; G11; G11C; G11C19/00; G11C19/28; G11C19/282; G11C19/285; G11C27/00; G11C27/04; H04; H04N; H04N25/00; H04N25/60; H04N25/63
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
238 words
Semiconductor apparatus which comprises: a. a semiconductor charge transfer device having a single input transfer device terminal and a single output transfer device terminal; b. an inverter having an inverter output terminal, said output device terminal connected to an input terminal of the inverter; c. a single input signal source terminal; d. an input feedback terminal; e. an output feedback terminal connected to the input feedback terminal; f. first electrical switching means for connecting the input device terminal in periodic alternate succession to one of the input signal source terminal and the input feedback terminal; g. second electrical switching means for connecting the inverter output terminal alternately to one of a utilization means terminal and the output feedback terminal which is connected to the input feedback terminal; and h. clock cycle means for producing periodic cycles of charge transfer in the device and for controlling the first and second switching means, each cycle comprising a phase from each of a first and second periodic sequence of clock phases, such that the inverter output terminal is connected to the input device terminal through the input feedback terminal during the first periodic sequence of clock phases and is connected to the utilization means during the second periodic sequence of clock phases interlaced with and complementary to the first sequence, and such that the input device terminal is connected to the input signal source during said second sequence of clock phases.
Claim 2
Dependent Claim
238 words
Semiconductor apparatus which comprises: a. a semiconductor charge transfer device having a single input transfer device terminal and a single output transfer device terminal; b. an inverter having an inverter output terminal, said output device terminal connected to an input terminal of the inverter; c. a single input signal source terminal; d. an input feedback terminal; e. an output feedback terminal connected to the input feedback terminal; f. first electrical switching means for connecting the input device terminal in periodic alternate succession to one of the input signal source terminal and the input feedback terminal; g. second electrical switching means for connecting the inverter output terminal alternately to one of a utilization means terminal and the output feedback terminal which is connected to the input feedback terminal; and h. clock cycle means for producing periodic cycles of charge transfer in the device and for controlling the first and second switching means, each cycle comprising a phase from each of a first and second periodic sequence of clock phases, such that the inverter output terminal is connected to the input device terminal through the input feedback terminal during the first periodic sequence of clock phases and is connected to the utilization means during the second periodic sequence of clock phases interlaced with and complementary to the first sequence, and such that the input device terminal is connected to the input signal source during said second sequence of clock phases.
Claim 3
Dependent Claim
16 words
Apparatus according to claim 1 in which the device is a linear path semiconductor transfer device.
Claim 4
Dependent Claim
18 words
Apparatus according to claim 2 in which the charge transfer device is integrated in a silicon semiconductor wafer.
Claim 5
Dependent Claim
47 words
Apparatus according to claim 1 in which the first sequence is essentially every other first number of half cycles, each cycle comprising a phase from each of the first and second sequence, and the device includes a serial-parallel-serial charge semiconductor device having the first number of columns.
Claim 6
Dependent Claim
213 words
Semiconductor apparatus which includes: a. a first semiconductor charge transfer device having a single first device's input terminal and a single first device's output terminal, said first device's output terminal being connected to an input terminal of a first inverter having a first inverter's output terminal; b. a second charge transfer device with a second similar set of single input and single output device terminals similarly connected to a similar second inverter; c. first electrical switching means for connecting the first device's input terminal to a single input signal source terminal during a first sequence of time intervals and to the first inverter's output terminal during a second sequence of time intervals interlaced and nonoverlapping with the first sequence; d. second electrical switching means for connecting the first inverter's output terminal to a utilization means terminal during the first sequence of time intervals when the first switching means connects the first device's input terminal to the single input signal source terminal, and for connecting the second inverter's output terminal to the utilization means during time intervals complementary to those of the first sequence; and e. third switching means for connecting the second device's input terminal to the second inverter's output terminal during time intervals complementary to the time intervals of the second sequence.
Claim 7
Dependent Claim
213 words
Semiconductor apparatus which includes: a. a first semiconductor charge transfer device having a single first device's input terminal and a single first device's output terminal, said first device's output terminal being connected to an input terminal of a first inverter having a first inverter's output terminal; b. a second charge transfer device with a second similar set of single input and single output device terminals similarly connected to a similar second inverter; c. first electrical switching means for connecting the first device's input terminal to a single input signal source terminal during a first sequence of time intervals and to the first inverter's output terminal during a second sequence of time intervals interlaced and nonoverlapping with the first sequence; d. second electrical switching means for connecting the first inverter's output terminal to a utilization means terminal during the first sequence of time intervals when the first switching means connects the first device's input terminal to the single input signal source terminal, and for connecting the second inverter's output terminal to the utilization means during time intervals complementary to those of the first sequence; and e. third switching means for connecting the second device's input terminal to the second inverter's output terminal during time intervals complementary to the time intervals of the second sequence.
Claim 8
Dependent Claim
18 words
Apparatus according to claim 5 in which the first and second devices are serial-parallel-serial types of transfer devices.
Claim 9
Dependent Claim
17 words
Apparatus according to claim 5 in which the first and second devices are linear path transfer devices.
Claim 10
Dependent Claim
21 words
Apparatus according to claim 5 in which the first and second charge transfer devices are integrated in a single semiconductor wafer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-15 | 1979-12-15 | 1980-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-15 | 1983-12-15 | 1984-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-15 | 1987-12-15 | 1988-06-15 | $7700.00 | Window Closed / Lapsed |