Pulse width and amplitude screening circuit

Claim 2

A pulse width and amplitude screening circuit to provide an output pulse for each input pulse whose amplitude and width fall within specified limits comprising: a first source of said analog input pulses; first means coupled to said first source to produce a first signal when the amplitude of one of said input pulses exceeds a first reference amplitude; second means coupled to said first source to produce a second signal when the width of said one of said input pulses has an amplitude exceeding a second reference amplitude different than said first reference amplitude; third means coupled to said second means to convert said second signal into a binary count, to produce a third signal when said count is greater than a minimum pulse width reference count and to produce a fourth signal when said count is less than a maximum pulse width reference count; and fourth means coupled to said first means and said third means responsive to the simultaneous presence of said first, third and fourth signals to produce said output pulse.

Claim 3

A circuit according to claim 1, wherein said first reference signal is a first voltage equal to an expected peak amplitude of an input pulse, and said second reference signal is a second voltage equal to an expected amplitude related to the width of an input pulse, said second voltage being less than said first voltage.

Claim 4

A circuit according to claim 1, wherein said first means includes a second source of voltage equal to said first reference amplitude, and an amplitude comparator coupled to said first and second sources to produce said first signal.

Claim 5

A circuit according to claim 1, wherein said second means includes a second source of voltage equal to said second reference amplitude, and an amplitude comparator coupled to said first and second sources to produce said second signal.

Claim 6

A circuit according to claim 1, wherein said third means includes a flip flop coupled to said second means, said flip flop changing state at the time of transistion of said second signal from a high condition to a low condition, a digital counter coupled to said second means, said counter being enabled at the time of transition of said second signal from a low condition to a high condition and disabled at the time of transition of said second signal from a high condition to a low condition, a second source of clock coupled to said counter to control the counting thereof, a time delay circuit coupled to said flip flop and said counter to reset said flip flop and said counter after a given time delay from the time said flip flop changes state, a first digital register storing a minimum pulse width reference count, a second digital register storing a maximum pulse width reference count, a first digital comparator coupled to said counter and said first register to produce said third signal, and a second digital comparator coupled to said counter and said second register to produce said fourth signal.

Claim 7

A circuit according to claim 1, wherein said fourth means includes a logic gate coupled to said first means and said third means to produce a gate signal in response to the simultaneous presence of said first, third and fourth signals, and a pulse generator coupled to said logic gate responsive to said gate signal to produce said output pulse.

Claim 8

A circuit according to claim 1, wherein said first means includes a second source of voltage equal to said first reference amplitude, and a first amplitude comparator coupled to said first and second sources to produce said first signal; said second means includes a third source of voltage equal to said second reference amplitude, and a second amplitude comparator coupled to said first and third sources to produce said second signal; said third means includes a flip flop coupled to said second amplitude comparator, said flip flop changing state at the time of transition of said second signal from a high condition to a low condition. a digital counter coupled to said second amplitude comparator, said counter being enabled at the time of transition of said second signal from a low condition to a high condition and disabled at the time of transition of said second signal from a high condition to a low condition, a fourth source of clock coupled to said counter to control the counting thereof, a time delay circuit coupled to said flip flop and said counter to reset said flip flop and said counter after a given time delay from the time said flip flop changes state, a first digital register storing a minimum pulse width reference count, a second digital register storing a maximum pulse width reference count, a first digital comparator coupled to said counter and said first register to produce said third signal, and a second digital comparator coupled to said counter and said second register to produce said fourth signal; and said fourth means includes a logic gate coupled to said first amplitude comparator, said first digital comparator and said second digital comparator to produce a gate signal in response to the simultaneous presence of said first, third and fourth signals, and a pulse generator coupled to said logic gate responsive to said gate signal to produce said output pulse.

Claim 9

A pulse width and amplitude screening system to provide a system output pulse for each analog input pulse whose amplitude and width fall within a given range of amplitudes and a given range of widths comprising: a first source of said analog input pulses; a plurality of pulse width and amplitude screening circuits, each of said circuits being coupled to said first source and providing a circuit output pulse for each analog input pulse whose amplitude and width fall within different specified limits covering said given range of amplitudes and widths, each of said circuits including first means coupled to said first source to produce a first signal when the amplitude of one of said input pulses exceeds a first reference amplitude, second means coupled to said first source to produce a second signal when the width of said one of said input pulses has an amplitude exceeding a second reference amplitude different than said first reference amplitude, third means coupled to said second means to convert said second signal into a binary count, to produce a third signal when said count is greater than a minimum pulse width reference count and to produce a fourth signal when said count is less than a maximum pulse width reference count, and fourth means coupled to said first means and said third means responsive to the simultaneous presence of said first, third and fourth signals to produce said circuit output pulse; said first and second reference amplitudes being different for each of said plurality of circuits extending from low amplitude values to high amplitude values to cover said given range of amplitudes and widths; a plurality of INHIBIT gates each coupled to a different one of said plurality of circuits and to one of said plurality of circuits having the next higher value for said first and second reference amplitudes when compared to the value for said first and second reference amplitudes of said different one of said plurality of circuits to inhibit said circuit output pulse of said different one of said plurality of circuits when said first signal is present at the output of said one of said plurality of circuits; and an OR gate coupled to each of said INHIBIT gates to provide said system output pulse from said circuit output pulse of said one of said plurality of circuits.

Claim 10

A pulse width and amplitude screening system to provide a system output pulse for each analog input pulse whose amplitude and width fall within a given range of amplitudes and a given range of widths comprising: a first source of said analog input pulses; a plurality of pulse width and amplitude screening circuits, each of said circuits being coupled to said first source and providing a circuit output pulse for each analog input pulse whose amplitude and width fall within different specified limits covering said given range of amplitudes and widths, each of said circuits including first means coupled to said first source to produce a first signal when the amplitude of one of said input pulses exceeds a first reference amplitude, second means coupled to said first source to produce a second signal when the width of said one of said input pulses has an amplitude exceeding a second reference amplitude different than said first reference amplitude, third means coupled to said second means to convert said second signal into a binary count, to produce a third signal when said count is greater than a minimum pulse width reference count and to produce a fourth signal when said count is less than a maximum pulse width reference count, and fourth means coupled to said first means and said third means responsive to the simultaneous presence of said first, third and fourth signals to produce said circuit output pulse; said first and second reference amplitudes being different for each of said plurality of circuits extending from low amplitude values to high amplitude values to cover said given range of amplitudes and widths; a plurality of INHIBIT gates each coupled to a different one of said plurality of circuits and to one of said plurality of circuits having the next higher value for said first and second reference amplitudes when compared to the value for said first and second reference amplitudes of said different one of said plurality of circuits to inhibit said circuit output pulse of said different one of said plurality of circuits when said first signal is present at the output of said one of said plurality of circuits; and an OR gate coupled to each of said INHIBIT gates to provide said system output pulse from said circuit output pulse of said one of said plurality of circuits.

Claim 11

A system according to claim 8, wherein each of said first means includes a second source of voltage equal to said first reference amplitude, and an amplitude comparator coupled to said first and second sources to produce said first signal.

Claim 12

A system according to claim 8, wherein each of said second means includes a second source of voltage equal to said second reference amplitude, and an amplitude comparator coupled to said first and second sources to produce said second signal.

Claim 13

A system according to claim 1, wherein each of said third means includes a flip flop coupled to said second means, said flip flop changing state at the time of transition of said second signal from a high condition to a low condition, a digital counter coupled to said second means, said counter being enabled at the time of transition of said second signal from a low condition to a high condition and disabled at the time of transition of said second signal from a high condition to a low condition, a second source of clock coupled to said counter to control the counting thereof, a time delay circuit coupled to said flip flop and said counter to reset said flip flop and said counter after a given time delay from the time said flip flop changes state, a first digital register storing a minimum pulse width reference count, a second digital register storing a maximum pulse width reference count, a first digital comparator coupled to said counter and said first register to produce said third signal, and a second digital comparator coupled to said counter and said second register to produce said fourth signal.

Claim 14

A system according to claim 8, wherein each of said fourth means includes a logic gate coupled to said first means and said third means to produce a gate signal in response to the simultaneous presence of said first, third and fourth signals, and a pulse generator coupled to said logic gate responsive to said gate signal to produce said output pulse.

Claim 15

A system according to claim 8, wherein each of said first means includes a second source of voltage equal to said first reference amplitude, and a first amplitude comparator coupled to said first and second sources to produce said first signal; each of said second means includes a third source of voltage equal to said second reference amplitude, and a second amplitude comparator coupled to said first and third sources to produce said second signal; each of said third means includes a flip flop coupled to said second amplitude comparator, said flip flop changing state at the time of transition of said second signal from a high condition to a low condition, a digital counter coupled to said second amplitude comparator, said counter being enabled at the time of transition of said second signal from a low condition to a high condition and disabled at the time of transition of said second signal from a high condition to a low condition, a fourth source of clock coupled to said counter to control the counting thereof, a time delay circuit coupled to said flip flop and said counter to reset said flip flop and said counter after a given time delay from the time said flip flop changes state, a first digital register storing a minimum pulse width reference count, a second digital register storing a maximum pulse width reference count, a first digital comparator coupled to said counter and said first register to produce said third signal, and a second digital comparator coupled to said counter and said second register to produce said fourth signal; and each of said fourth means includes a logic gate coupled to said first amplitude comparator, said first digital comparator and said second digital comparator to produce a gate signal in response to the simultaneous presence of said first, third and fourth signals, and a pulse generator coupled to said logic gate responsive to said gate signal to produce said output pulse.