US3958243A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for generating a digital or analog signal as a function of doppler frequency
Assignee: United States Department of the Navy
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Filing: 1975-03-20
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Granted: 1976-05-18
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Expires: 1995-03-20
Abstract
Abstract A control circuit having a digital memory for providing sweep voltages to ceivers in a doppler satellite tracking station of proper amplitude and duration to ensure searching in the correct doppler frequency range. An internally generated ramp function voltage is combined with a reference voltage to produce a composite sweep signal for the receiver. The reference voltage level is determined either from a set of digi-switches or from a digital memory circuit which outputs a digital signal that is a function of the frequency of a received doppler signal.
Inventors
- 👤 John L. Linder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:42
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/66; G01S11/00; G01S11/02; G01S11/10; G01S13/02; G01S13/50; G01S13/58; G01S13/585; G01S13/586; H; H03; H03K; H03K4/00; H03K4/06; H03K4/08; H03K4/48
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
458 words
A circuit for generating an analog voltage that is a function of the frequency of a received doppler signal in a doppler satellite tracking station comprising: a. a multiple-bit counter circuit having a first and a second input and a plurality of outputs; b. means for providing a doppler frequency signal having an output; c. a first gate circuit having an output and a first and a second input, said output being connected to said first input of said counter circuit, said first input of said gate circuit being connected to said output of said means for providing a doppler frequency signal; d. a storage register having a plurality of inputs connected to said plurality of outputs of said counter circuit such that said counter circuit and said storage register are in parallel, said storage register having a plurality of outputs, said plurality of outputs being a binary digital signal that is a function of the frequency of said doppler-frequency signal, said storage register also having a clock input; e. a digital-to-analog converter circuit having an input circuit and an output, said output being said analog voltage; f. means for providing an enable signal; g. means for gating in parallel said binary digital signal from said plurality of outputs of said storage register to said input circuit of said digital-to-analog converter input circuit whenever said enable signal is present, said enable signal being connected to said means for gating; h. means for providing a low-frequency signal having an output; i. means for providing a doppler-frequency correlation signal having an output; j. a circuit for generating control signals having a low-frequency signal input, a doppler-frequency correlation input, a gate signal output, a reset signal output, and a clock signal output, said low-frequency input being connected to said output of said means for providing a low-frequency signal, said doppler-frequency correlation input being connected to said output of said means for providing a doppler-frequency correlation signal, said gate signal output being connected to said second input of said gate circuit whereby said gate circuit is enabled when a control signal is at a logic 1 level on said gate signal output, said reset signal output being connected to said second input to said counter circuit whereby said counter circuit is reset when a control signal is present on said reset signal output, said clock signal output being connected to said clock input of said storage register wherein said storage register shifts the contents of said counter circuit into itself only when a control signal is present on said clock signal output, thereby said storage register remembers said digital signal that is a function of the frequency of said doppler-frequency signal until a control signal is present on said clock signal output.
Claim 2
Dependent Claim
458 words
A circuit for generating an analog voltage that is a function of the frequency of a received doppler signal in a doppler satellite tracking station comprising: a. a multiple-bit counter circuit having a first and a second input and a plurality of outputs; b. means for providing a doppler frequency signal having an output; c. a first gate circuit having an output and a first and a second input, said output being connected to said first input of said counter circuit, said first input of said gate circuit being connected to said output of said means for providing a doppler frequency signal; d. a storage register having a plurality of inputs connected to said plurality of outputs of said counter circuit such that said counter circuit and said storage register are in parallel, said storage register having a plurality of outputs, said plurality of outputs being a binary digital signal that is a function of the frequency of said doppler-frequency signal, said storage register also having a clock input; e. a digital-to-analog converter circuit having an input circuit and an output, said output being said analog voltage; f. means for providing an enable signal; g. means for gating in parallel said binary digital signal from said plurality of outputs of said storage register to said input circuit of said digital-to-analog converter input circuit whenever said enable signal is present, said enable signal being connected to said means for gating; h. means for providing a low-frequency signal having an output; i. means for providing a doppler-frequency correlation signal having an output; j. a circuit for generating control signals having a low-frequency signal input, a doppler-frequency correlation input, a gate signal output, a reset signal output, and a clock signal output, said low-frequency input being connected to said output of said means for providing a low-frequency signal, said doppler-frequency correlation input being connected to said output of said means for providing a doppler-frequency correlation signal, said gate signal output being connected to said second input of said gate circuit whereby said gate circuit is enabled when a control signal is at a logic 1 level on said gate signal output, said reset signal output being connected to said second input to said counter circuit whereby said counter circuit is reset when a control signal is present on said reset signal output, said clock signal output being connected to said clock input of said storage register wherein said storage register shifts the contents of said counter circuit into itself only when a control signal is present on said clock signal output, thereby said storage register remembers said digital signal that is a function of the frequency of said doppler-frequency signal until a control signal is present on said clock signal output.
Claim 3
Dependent Claim
129 words
The generator of claim 1 wherein said circuit for generating control signals comprises: a. a flip-flop having an input and a first and a second output, said input being connected to said output of said means for providing a low-frequency signal, said first output being said gate signal output; b. a monostable multivibrator having an input and an output, said input being connected to said second output of said flip-flop, said output being said reset signal output; c. a second gate circuit having a first and a second input and an output, said first input being connected to said second output of said flip-flop, said second input being connected to said output of said means for providing a doppler frequency correlation signal, said output being said clock signal output.
Claim 4
Dependent Claim
27 words
The generator of claim 2 wherein said plurality of outputs of said multiple-bit counter are fewer in number than the number of bits of said multiple-bit counter.
Claim 5
Dependent Claim
393 words
A circuit for generating a binary digital signal that is a function of the frequency of a received doppler signal in a doppler satellite tracking station comprising: a. a multiple-bit counter circuit having a first and a second input and a plurality of outputs; b. means for providing a doppler frequency signal having an output; c. a first gate circuit having an output and a first and a second input, said output being connected to said first input of said counter circuit, said first input of said gate circuit being connected to said output of said means for providing a doppler frequency signal; d. a storage register having a plurality of inputs connected to said plurality of outputs of said counter circuit such that said counter circuit and said storage register are in parallel, said storage register having a plurality of outputs, said plurality of outputs being said binary digital signal that is a function of the frequency of said doppler frequency signal, said storage register also having a clock input; e. means for providing a low-frequency signal having an output; f. means for providing a doppler-frequency correlation signal having an output; g. a circuit for generating control signals having a low-frequency signal input, a doppler frequency correlation input, a gate signal output, a reset signal output and a clock signal output, said low-frequency input being connected to said output of said means for providing a low-frequency signal, said doppler frequency correlation input being connected to said output of said means for providing a doppler frequency correlation signal, said gate signal output being connected to said second input of said gate circuit whereby said gate circuit is enabled when a control signal is at a logic 1 level on said gate signal output, said reset signal output being connected to said second input to said counter circuit whereby said counter circuit is reset when a control signal is present on said reset signal output, said clock signal output being connected to said clock input of said storage register wherein said storage register shifts the contents of said counter circuit into itself only when a control signal is present on said clock signal output, thereby said storage register remembers said digital signal that is a function of the frequency of said doppler-frequency signal until a control signal is present on said clock signal output.
Claim 6
Dependent Claim
393 words
A circuit for generating a binary digital signal that is a function of the frequency of a received doppler signal in a doppler satellite tracking station comprising: a. a multiple-bit counter circuit having a first and a second input and a plurality of outputs; b. means for providing a doppler frequency signal having an output; c. a first gate circuit having an output and a first and a second input, said output being connected to said first input of said counter circuit, said first input of said gate circuit being connected to said output of said means for providing a doppler frequency signal; d. a storage register having a plurality of inputs connected to said plurality of outputs of said counter circuit such that said counter circuit and said storage register are in parallel, said storage register having a plurality of outputs, said plurality of outputs being said binary digital signal that is a function of the frequency of said doppler frequency signal, said storage register also having a clock input; e. means for providing a low-frequency signal having an output; f. means for providing a doppler-frequency correlation signal having an output; g. a circuit for generating control signals having a low-frequency signal input, a doppler frequency correlation input, a gate signal output, a reset signal output and a clock signal output, said low-frequency input being connected to said output of said means for providing a low-frequency signal, said doppler frequency correlation input being connected to said output of said means for providing a doppler frequency correlation signal, said gate signal output being connected to said second input of said gate circuit whereby said gate circuit is enabled when a control signal is at a logic 1 level on said gate signal output, said reset signal output being connected to said second input to said counter circuit whereby said counter circuit is reset when a control signal is present on said reset signal output, said clock signal output being connected to said clock input of said storage register wherein said storage register shifts the contents of said counter circuit into itself only when a control signal is present on said clock signal output, thereby said storage register remembers said digital signal that is a function of the frequency of said doppler-frequency signal until a control signal is present on said clock signal output.
Claim 7
Dependent Claim
128 words
The generator of claim 4 wherein said circuit for generating control signals comprises: a. a flip-flop having an input and a first and a second output, said input being connected to said output of said means for providing a low-frequency signal, said first output being said gate signal output; b. a monostable multivibrator having an input and an output, said input being connected to said second output of said flip-flop, said output being said reset signal output; c. a second gate circuit having a first and a second input and an output, said first input being connected to said second output of said flip-flop, said second input being connected to said output of said means for providing a doppler-frequency correlation signal, said output being said clock signal output.
Claim 8
Dependent Claim
27 words
The generator of claim 5 wherein said plurality of outputs of said multiple-bit counter are fewer in number than the number of bits of said multiple-bit counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-05-18 | 1979-11-17 | 1980-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-05-18 | 1983-11-17 | 1984-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-05-18 | 1987-11-17 | 1988-05-18 | $7700.00 | Window Closed / Lapsed |