Roll and pitch correction for a fixed-antenna doppler system

Claim 2

Apparatus to transform the outputs of a fixed-antenna doppler system, said outputs being frequencies proportional to the velocity along the three body axes of an aircraft in which the system is installed, into two signals representing velocities along the ground, one a velocity in the direction of heading and another the drift velocity normal thereto, there being available in the aircraft voltages representing the sines and cosines of the pitch and roll of the aircraft, the transformation being capable of being expressed by two equations each comprised of terms some of which are said body axes velocities and some of which are the product of one of said body axes velocities and a trigonometric function Including at least one of said pitch and roll sines and cosines said apparatus comprising: a. a plurality of circuit means to provide DC voltages proportional to each required trigonometric function; b. means to develop a reference DC voltage whose relative value as compared to said trigonometric function voltages is one; c. a plurality of clipper-multipliers and bucket counter units, one being provided for each term in each of said equations, each having as one input one of the frequencies representing a body axis velocity and as another input one of said DC proportional and reference voltages and each providing an output current which is proportional to the product of its two inputs; d. first means to sum the outputs of the clipper-multiplier and bucket counter units having products representing the terms of the equation expressing heading velocity; and e. second means to sum the output of the clipper-multiplier and bucket counter units having products representing the terms of the equation expressing drift velocity.

Claim 3

The invention according to claim 1 wherein said first and second summing means comrise first and second operational amplifiers and further including for each of said first and second amplifiers: a. a voltage to frequency converter having as an input the amplifier output; b. a further clipper-multiplier and bucket counter unit having the output of said converter as one input and said DC reference voltage as another input and providing its output as a further input to be summed by said amplifier whereby closed loop operation will result.

Claim 4

The invention according to claim 2 wherein each of said frequencies provided by said doppler system is provided as a first frequency output when the velocity is in a positive direction and as a second frequency output when the velocity is in a negative direction and wherein each of said bucket counter clipper multiplier units comprises at least a pair of clipper-multiplier bucket counters, one clipper multiplier bucket counter having the frequency proportional to a positive velocity as an input and the other clipper multiplier bucket counter having the frequency proportional to a negative velocity as an input, said one clipper multiplier bucket counter being arranged to provide current in a first direction and said other clipper multiplier bucket counter being arranged to provide current in the opposite direction and wherein said voltage to frequency converter provides a first frequency output for a positive output from said amplifier and a second frequency output for a negative output from said amplifier; and said further clipper multiplier bucket counter comprises a pair of clipper multiplier bucket counters, one having said first frequency output as an input and providing a feed back current in said second direction and the other having said second frequency output as an input and providing a feedback current in said first direction.

Claim 5

The invention according to claim 3 wherein each of said clipper-multiplier bucket counter units having as another input one of said D.C. voltages proportional to said trigonemetric functions comprises: a. a first clipper-multiplier bucket counter having said first frequency output and said D.C. reference as inputs and providing an output current in a first direction which is proportional their product; b. a second clipper-multiplier bucket counter having said first frequency output, said D.C. reference voltage and one of said proportional voltages as inputs and providing an output current in an opposite direction which is proportional to the difference between said D.C. reference voltage and said one proportional voltage times said first frequency; c. a third clipper-multiplier bucket counter having said second frequency output and said D.C. reference as inputs and providing an output current in said opposite direction which is proportional to the product of said inputs; d. a fourth clipper-multiplier buckeT counter having said second frequency output, said D.C.reference voltage and said one proportional voltage as inputs and providing an output current in said first direction which is proportional to the difference between said D.C. reference voltage and said one proportional voltage times said second frequency.

Claim 6

The invention according to claim 1 wherein said heading velocity is expressed as VH VX- VZ cos RsinP - 1/2 Vx sinPtanP +VytanPsinR and said drift velocity as VD VY + VZ sinR- 1/2 VYtanRsinR and said circuit means to provide DC voltages comprise: a. a multiplying demodulator having sin R, cos R and sin P as inputs and providing sin P cos R as an output; b. a first sampling multiplier-divider having sin P, cos P and sin R as inputs and providing tan P sin R as an output; c. a second sampling multiplier-divider having sin P, cos P and sin P as inputs and providing - 1/2 tan P sin P as an output; d. a first phase sensitive demodulator having sin R as an input and providing a DC value proportional thereto as an output; e. a third sampling multiplier-divider having sin R, cos R and sin R as inputs and providing - 178 tan R sin R as an output: said means to develop a reference DC voltage comprises: f. a second phase sensitive demodulator for having the reference AC voltage as an input; and said plurality of clipper multiplier units comprise: g. a first clipper-multiplier unit and bucket counter having the frequency proportional to VX and said reference DC voltage as inputs; h. a second clipper-multiplier and bucket counter unit having the frequency proportional to VZ and the output of said multiplying demodulator as inputs; i. a third clipper-multiplier and bucket counter unit having the frequency proportional to VX and the output of said second sampling multiplier-divider as inputs; j. a fourth clipper-multiplier and bucket counter unit having the frequency proportional to VY and the output of said first sampling multiplier-divider as inputs; k. a fifth clipper-multiplier and bucket counter unit having the frequency proportional to VY and said DC reference voltage as inputs; l. a sixth clipper-multiplier and bucket counter unit having the frequency proportional to VZ and the output of said first phase sensitive demodulator as inputs; m. a seventh clipper-multiplier and bucket counter unit having the frequency proportional to VY and the output of said third ampling multiplier-divider as input; n. the outputs of said first, second, wherein each and fourth clipper-multipliers and bucket counter units being summed in said first summing means; and o. the outputs of said fifth, sixth and seventh clipper-multipliers and bucket counter units being summed in said second summing means.

Claim 7

The invention according to claim 5 wherein said first and second summing means comprise first and second operational amplifiers and further including for each of said first and second amplifiers; a. a voltage to frequency converter having as an input the amplifier output; b. a further clipper-multiplier and bucket counter unit having the output of said converter as one input and said DC reference voltage as another input and providing its output as a further input to be summed by said amplifier whereby closed loop operation will result.

Claim 8

The invention according to claim 5 wherein in said multiplying demodulator comprises: a. a 90* phase shifter having as an input sine R; b. means to sum the output of said phase shifter with cosine R; c. a phase sensitive demodulator having sine P as a signal input and the output of said summing means as a switching input and providing as a DC output the value of its signal input averaged over the period during which said switching input is present.

Claim 9

The invention according to claim 7 wherein said summing means comprises an operational amplifier.

Claim 10

The invention according to claim 5 where the inputs to each of said sampling multiplier-dividers may be considered respectively as X, Y, and Z, the instantaneous values of said quantities being respectively X sin omega t, Y sin omega t and Z sin omega t, and wherein each of said sampling multiplier-divider comprises: a. a phase sensitive demodulator having Y sin omega t as an input and providing a DC value of Y proportional to the RMS value of said input as an output; and b. means having said DC output and X sin omega t as inputs and adapted to sample and store the instantaneous value of Z sin omega t at the pont where sin omega t equals theta which occurs when the instantaneous value of X sin omega t becomes equal to the DC value of Y while going in the positive direction at which point X sin Theta equals Y and the sampled value will be Z sin theta or, substituting for sin theta, will be Z times Y divided by X.

Claim 11

The invention according to claim 9 wherein said means to sample and store comprise; a. comparator means having said DC output as a first input and X sine omega t as a second input and arranged to supply a pulse output when the value of X sine omega t reaches equality with said DC value when going in a positive direction; b. switching means having Z sin omega t as an input and responsive to said pulse to provide said input as an output at the occurrence of said pulse; and c. means to store the output of said switching means.

Claim 12

The invention according to claim 10 wherein said comparator comprises a differential amplifier having a capacitor in series with its output, said switching means comprises a transistor, said storage means comprises a capacitor and further including a unity gain amplifier interposed between said capacitor and the circuit output to avoid discharging said capacitor.

Claim 13

The invention according to claim 11 wherein each of said frequencies provided by said doppler system is provided as a first frequency output when the velocity is in a positive direction and as a second frequency output when the velocity is in a negative direction, and wherein each of said bucket counter clipper-multiplier units comprises at least a pair of clipper-multiplier bucket counters, one clipper-multiplier bucket counter having the frequency proportional to a positive velocity as an input and another clipper-multiplier bucket counter having the frequency proportional to the negative velocity as an input, said one clipper-multiplier bucket counter being arranged to provide current in a first direction and said other clipper-multiplier bucket counter being arranged to provide current in the opposite direction and wherein said voltage to frequency converter provides a first frequency output for a positive output from said amplifier and a second frequency output for a negative output from said amplifier; and said further clipper-multiplier bucket counter comprises a pair of clipper-multiplier bucket counters one having said first frequency output as an input and providing a feed back current in said second direction and the other having said second frequency output as an input and providing a feedback current in said first direction.

Claim 14

The invention according to claim 12 where each of said clipper-multiplier bucket counter units having as another input one of the said D.C. voltages proportional to said trigonometric functions comprises: a. a first clipper-multiplier bucket counter having said first frequency output and said D.C. reference as inputs and providing an output current in a first direction which is proportional their product; b. a second clipper-multiplier bucket counter having said first frequency output, said D.C. reference voltage and one of said proportional voltages as inputs and providing an output cuRrent in an opposite direction which is proportional to the difference between said D.C. reference voltage and said one proportional voltage time said first frequency; c. a third clipper-multiplier bucket counter having said second frequency output and said D.C. reference as inputs and providing an output current in said opposite direction which is proportional to the product of said inputs; d. a fourth clipper-multiplier bucket counter having said second frequency output, said D.C. reference voltage and said one proportional voltage as inputs and providing an output current in said first direction which is proportional to the difference between said D.C. reference voltage and said one proportional voltage times said second frequency.

Claim 15

The invention according to claim 1 wherein said heading velocity is expressed as: VH VX - VZ cos R sinP (-Vx sin2P/1+cosP) + VY sinRsinP and said drift velocity as: VD VY +Vz sin R- VY (sin2R/1+cosR) and said circuit means to provide said DC voltages comprise: a. a multiplying demodulator having sin R cos R and sin P as inputs and providing sin P cos R as an output; b. a first sampling multiplier-divider having sin P, the reference AC voltage, and sin R as inputs and providing as an output sin R sin P; c. a second sampling multiplier-divider having sin P, 1 + cos P and sin P as inputs and providing an output which is equal to sin2P over 1+ cos P; d. A first phase sensitive demodulator having sin R as an input and providng a DC value proportional thereto as an output; e. a third sampling multiplier-divider having sin R, 1cos R and sin R as inputs and providing as an output sin2R divided by 1+ cos R; said means to develop a DC reference voltage comprises; f. a second phase sensitive demodulator having the reference AC voltage as n input; and said plurality of clipper-multiplier and bucket counter units comprise: g. a first clipper-multiplier and bucket counter unit having the frequency proportional to VX and said reference DC voltage as such inputs; h. a second clipper-multiplier and bucket counter unit having the frequency proportional to VZand the output of said multiplying demodulator as inputs; i. a third clipper-multiplier and bucket counter unit having the frequency proportional to VX and the output of said second sampling multiplier-divider as inputs; j. a fourth clipper-multiplier bucket counter unit having the frequency proportional to VY and the output of said first sampling multiplier-divider as inputs; k. a fifth clipper-multiplier and bucket counter unit having the frequency proportional to VY and said DC reference voltage as inputs; l. a sixth clipper-multiplier and bucket counter unit having the frequency proportional to VZand the output of said first phase sensitive demodulator as inputs; m. a seventh clipper-multiplier and bucket counter unit having the frequency proportional to VY and the output of said third sampling multiplier-divider as inputs; n. the outputs of said first, second, third and fourth clipper-multiplier and bucket counter units being summed in said first summing means; and o. the outputs of said fifth, sixth and seventh clipper-multipliers and bucket counter units being summed in said second summing means.

Claim 16

The invention according to claim 14 wherein said first and second summing means comprises first and second operational amplifiers and further including for each of said first and second amplifiers: a. a voltage to frequency converter having as an input the amplifier output; b. a further clipper-multiplier and bucket counter unit having the output of said converter as one input and Said DC reference voltage as another input and providing its output as a further input to be summed by said amplifier whereby closed loop operation will result.

Claim 17

The invention according to claim 15 wherein said multiplying demodulator comprises: a. a 90* phase shifter having as an input sine R; b. means to sum the output of said phase shifter with cosine R; c. a phase sensitive demodulator having sine P as a signal input and the output of said summing means as a switching input and providing as a D.C. output the value of its signal input averaged over the period during which said switching input is present.

Claim 18

The invention according to claim 16 wherein said summing means comprises an operational amplifier.

Claim 19

The invention according to claim 15 where the inputs of each of said sampling multiplier-dividers may be considered respectively as X, Y and Z, the instantaneous values of said quantities being respectively X sin omega t, Y sin t and Z sin omega t, and wherein each of said sampling multiplier-divider comprises: a. a phase sensitive demodulator having Y sin omega t as an input and providing a D.C. value of Y proportional to the RMS value of said input as an output; and b. means having said D.C. output and X sin omega t as inputs and adapted to sample and store the instantaneous value of Z sin omega t at the point where sin omega t equals theta which occurs when the instantaneous value of X sin omega t becomes equal to the D.C. value of Y while going in the positive direction at which point X sin Theta equals Y and the sample value will be Z sin theta or, substituting for sin theta, will be Z times Y divided by X.

Claim 20

The invention according to claim 18 wherein said means to sample and store comprise; a. comparator means having said D.C. output as a first input and X sine omega t as a second input and arranged to supply a pulse output when the value of X sin omega t reaches equality with said D.C. value when going in a positive direction; b. switching means having Z sine omega t as an input and responsive to said pulse to provide said input as an output at the occurrence of said pulse; and c. means to store the output of said switching means.

Claim 21

The invention according to claim 19 wherein said comparator comprises a differential amplifier having a capacitor in series its output, said switching means comprises a transistor, said storage means comprises a capacitor and further including a unity gain amplifier interposed between said capacitor and the circuit output to avoid discharging said capacitor.

Claim 22

The invention according to claim 20 whereieach of said frequencies provided by said doppler system is provided as a first frequency output when the velocity is in a positive direction and as a second frequency output when the velocity is in a negative direction, and wherein each of said bucket counter clipper-multiplier units comprises at least a pair of clipper-multiplier bucket counters, one clipper-multiplier bucket counter having the frequency proportional to a positive velocity as an input and another clipper-multiplier bucket counter having the frequency proportional to the negative velocity as an input, said one clipper-multiplier bucket counter being arranged to provide current in a first direction and said other clipper-multiplier bucket counter being arranged to provide current in the opposite direction and wherein said voltage to frequency converter provides a first frequency output for a positive output from said amplifier and a second frequency output for a negative output from said amplifier and said further clipper-multiplier bucket counter comprise a pair of clipper-multiplier bucket counters, one having said first frequency output as an input and providing a feed back current in said second direction and the other having said second frequency output as an input and providing a feed back current in said first direction.

Claim 23

The invention accOrding to claim 21 wherein each of said clipper-multiplier bucket counter units having as another input one of said D.C. voltages proportional to said trigonometric functions comprises: a. a first clipper-multiplier bucket counter having said first frequency output and said D.C. reference as inputs and providing an output current in a first direction which is proportional their product; b. a second clipper-multiplier bucket counter having said first frequency output, said D.C. reference voltage and one of said proportional voltages as inputs and providing an output current in an opposite direction which is proportional to the difference between said D.C. reference voltage and said one proportional voltage time said first frequency; c. a third clipper-multiplier bucket counter having said second frequency output and said D.C. reference as inputs and providing an output current in said opposite direction which is proportional to the product of said inputs; d. a fourth clipper-multiplier bucket counter having said second frequency output, said D.C. reference voltage and said one proportional voltage as inputs and providing an output current in said first direction which is proportional to the difference between said D.C. reference voltage and said one proportional voltage times said second frequency.