Eliminating dc-dc converter switching transients in digital systems

Claim 2

In conjunction with a digital system wherein data representation depends at least in part on a fixed frequency signal, a power supply system comprising: means for converting a D.C. supply voltage to a second D.C. voltage level, said means employing an intermediate A.C. stage producing switching transients of a type normally deleterious to said data representation; and means for controlling switching within said A.C. stage to occur only in synchronization with switching of said fixed frequency signal to confine said transients to transition times in said fixed frequency signal.

Claim 3

The power supply of claim 1 wherein said controlling means comprises: means for producing a a buffered replica of said fixed frequency signal; means for dividing said buffered replica to produce a divided frequency signal wherein transitions occur only in synchronization with transitions in said fixed frequency signal; and means receiving an input of said divided frequency signal for controlling said switching within said A.C. stage to occur only in synchronization with said transitions in said divided frequency signal.

Claim 6

A power supply system for operation at a controlled frequency in synchronization with a second frequency in a digital system comprising: buffer means for providing a buffered signal at said second frequency; a frequency divider for dividing the frequency of said buffered signal to produce a divided signal; a flip-flop receiving the divided signal and having first and second alternately excited outputs; a first driver transistor having its base excited by said first output; a second driver transistor having its base excited by said second output; and a D.C. to D.C. converter having a transformer and first and second switching transistors, the base of said first switching transistor being driven by the collector of said first driver transistor and the base of said second switching transistor being driven by the collector of said second driver transistor, the collector of each of said first and second switching transistors being connected to the respective first terminal of the first and second primary coils of said transformer, the respective second terminal of each of said coils being connected at a common point to a D.C. supply voltage, said bases of said first and second switching transistors being respectively connected through first and second resistors to the respective first terminals of first and second feedback coils of said transformer, the respective second terminals of said first and second feedback coils each being grounded through a diode.

Claim 7

A power supply system for operation at a controlled frequency in synchronization with a second frequency in a digital system comprising: buffer means for providing a buffered signal at said second frequency; a frequency divider for dividing the frequency of said buffered signal to produce a divided signal; a flip-flop receiving the divided signal and having first and second alternately excited outputs; a first driver transistor having its base excited by said first output; a second driver transistor having its base excited by said second output; and a D.C. to D.C. converter having a transformer and first and second switching transistors, the base of said first switching transistor being driven by the collector of said first driver transistor and the base of said second switching transistor being driven by the collector of said second driver transistor, the collector of each of said first and second switching transistors being connected to the respective first terminal of the first and second primary coils of said transformer, the respective second terminal of each of said coils being connected at a common point to a D.C. supply voltage, said bases of said first and second switching transistors being respectively connected through first and second resistors to the respective first terminals of first and second feedback coils of said transformer, the respective second terminals of said first and second feedback coils each being grounded through a diode.

Claim 8

The power supply system of claim 4 wherein the respective bases of said first and second driver transistors are grounded through respective first and second resistors, wherein said bases are further respectively connected to said first and second flip-flop outputs through respective first and second capacitors and wherein the collectors of said driver transistors are respectively connected to said first and second switching transistor bases through respective first and second Shottky diodes.

Claim 9

The power supply system of claim 5 further including a broad band, low impedance capacitance connected between said connection point and ground.

Claim 10

A power supply for a digital system including a system clock producing periodic system clock pulses of a first fixed duration comprising: D.c. to D.C. conversion means employing an intermediate A.C. stage including first and second switching means producing deleterious switching transients; buffer means receiving an input from said system clock for outputting a buffered analog signal of said system clock pulse signal; frequency divider means for dividing said buffered analog signal to produce a divided signal, said divided signal comprising periodic pulses having a duration which is multiple of that of said first fixed duration; and driver means receiving an input of said divided signal for alternately exciting said first switching means and said second switching means in synchronization with the said divided signal pulses.

Claim 11

A power supply for a digital system including a system clock producing periodic system clock pulses of a first fixed duration comprising: D.c. to D.C. conversion means employing an intermediate A.C. stage including first and second switching means producing deleterious switching transients; buffer means receiving an input from said system clock for outputting a buffered analog signal of said system clock pulse signal; frequency divider means for dividing said buffered analog signal to produce a divided signal, said divided signal comprising periodic pulses having a duration which is multiple of that of said first fixed duration; and driver means receiving an input of said divided signal for alternately exciting said first switching means and said second switching means in synchronization with the said divided signal pulses.

Claim 12

The power supply of claim 7 wherein said divider means comprises a Modulo-N divider.

Claim 13

The power supply of claim 8 wherein the divisor N of said divider equals the ratio of the frequency of said clock signal to twice the synchronized operating frequency of said converter.

Claim 14

The power supply of claim 7 wherein said first and second switching means comprise first and second switching transistors, respectively, and said driving means comprises: a flip-flop receiving an input of said divided signal and having first and second outputs alternately excited by said divided signal; a first driver transistor having its base connected to said first flip-flop output and its collector connected for driving said first switching transistor; and a second driver transistor having its base connected to said second flip-flop output and its collector connected for driving said second switching transistor.

Claim 15

The power supply of claim 10 wherein said D.C. to D.C. conversion means further includes transformer means for forming an oscillator with said first and second switching transistors, said oscillator having a free-running frequency lower than said divided signal frequency.

Claim 16

The power supply of claim 11 wherein said divider means comprises a Modulo-N divider.

Claim 17

The power supply of claim 12 wherein the divisor N of said divider equals the ratio of the frequency of said clock signal to twice the synchronized operating frequency of said converter.

Claim 18

In conjunction with a digital system wherein data representation depends at least in part on a first periodic pulse signal, a power supply system comprising: a power converter employing an intermediate A.C. stage; means for producing a second periodic pulse signal, the pulses of said second periodic pulse signal having a duration which is a multiple of the duration of the pulses of said first periodic pulse signal; and means for controlling switching in said intermediate A.C. stage to be in synchronization with transitions in said second periodic pulse signal.

Claim 19

In conjunction with a digital system wherein data representation depends at least in part on a first periodic pulse signal, a power supply system comprising: a power converter employing an intermediate A.C. stage; means for producing a second periodic pulse signal, the pulses of said second periodic pulse signal having a duration which is a multiple of the duration of the pulses of said first periodic pulse signal; and means for controlling switching in said intermediate A.C. stage to be in synchronization with transitions in said second periodic pulse signal.

Claim 20

In conjunction with a digital system wherein data representation depends at least in part on a fixed frequency signal, a power supply system comprising: means for converting a D.C. supply voltage to a second D.C. voltage level, said means employing an intermediate A.C. stage producing switching transients of a type normally deleterious to said data representation; and means for confining the occurrence of said transients to transition times in said fixed frequency signal.

Claim 21

In conjunction with a digital system wherein data representation depends at least in part on a fixed frequency signal, a power supply system comprising: means for converting a D.C. supply voltage to a second D.C. voltage level, said means employing an intermediate A.C. stage producing switching transients of a type normally deleterious to said data representation; and means for confining the occurrence of said transients to transition times in said fixed frequency signal.

Claim 24

In a digital system employing a fixed frequency system clock and a D.C. - A.C. - DC. power converter in which transients occur, a method for preventing converter switching transients from affecting digital data patterns within said system, said method comprising the steps of: providing a switching signal of a predetermined frequency which is a submultiple of said system clock frequency; and applying said switching signal to said power converter to switch said power converter at a synchronized submultiple of said system clock frequency.

Claim 25

In a digital system employing a fixed frequency system clock and a D.C. - A.C. - DC. power converter in which transients occur, a method for preventing converter switching transients from affecting digital data patterns within said system, said method comprising the steps of: providing a switching signal of a predetermined frequency which is a submultiple of said system clock frequency; and applying said switching signal to said power converter to switch said power converter at a synchronized submultiple of said system clock frequency.