Numeral output system for circulating register

Claim 2

A numeral output system for a register comprising: a first register having a plurality of digit states for storing therein at least binary coded output numeral information; a second register for storing sequentially therein one digit of the binary coded output numeral information from said first register; output means for visually displaying the binary coded output numeral information of said second register; and means for providing a blanking time between adjacent binary coded output numeral signals which are transferred from said second register to said output means, for blanking the visual display of said output means during intervals between said adjacent signals.

Claim 3

A numeral output system for a register according to claim 1 further comprising: means for detecting an insignificant zero in said first register and to suppress said insignificant zero, whereby said zero is not displayed on said output means.

Claim 4

A numeral output system for a register according to claim 2 wherein said insignificant zero detecting means is included in said blanking means.

Claim 5

A numeral output system for a register according to claim 1 further comprising: control means for controlling the storage of one digit of the binary coded output numeral information from said first register in said second register during at least more than one digit time.

Claim 6

A numeral output system for a register according to claim 1 wherein said output means comprises a multi-digit numeral display device.

Claim 7

A numeral output system for a register according to claim 1 wherein said first register comprises a plurality of digit stages each being connected in series together and having a four bit parallel configuration, and said first register has a circulating loop.

Claim 8

A numeral output system for a register according to claim 2 wherein said insignificant zero detecting means includes at least one flip-flop circuit.

Claim 9

A numeral output system for a register according to claim 4 wherein said control means includes a timing pulse generator and gate means.

Claim 10

A numeral output system for a register comprising: a first register having a plurality of digit stages for storing therein at least binary coded output numeral information; output means for visually displaying the binary coded output numeral information of said first register; and means for developing a control signal for every digit, said control signal having a first signal level during which transferring of the output numeral information to said output means is inhibited and having a second signal level during which transferring of the output numeral information to said output means is permitted.

Claim 11

A numeral output system for a register comprising: a first register having a plurality of digit stages for storing therein at least binary coded output numeral information; output means for visually displaying the binary coded output numeral information of said first register; and means for developing a control signal for every digit, said control signal having a first signal level during which transferring of the output numeral information to said output means is inhibited and having a second signal level during which transferring of the output numeral information to said output means is permitted.

Claim 12

A numeral output system for a register according to claim 9 further comprising: means for detecting an insignificant zero in said first register and to suppress said insignificant zero, whereby said zero is not displayed on said output means.

Claim 13

A numeral output system for a register according to claim 10, wherein said insignificant zero detecting means is included in said control signal developing means.

Claim 14

A numeral output system for a register according to claim 9 further comprising: a second buffer register for storing sequentially therein one digit of the binary output numeral information from said first register, the output signal of said second register being controlled by the control signal from said control signal developing means.

Claim 15

A numeral output system for a register according to claim 9 wherein said output means comprises a multi-digit numeral display device.

Claim 16

A numeral output system for a register according to claim 9 wherein said output means comprises a printer.

Claim 17

A numeral output system for a register according to claim 12 further comprising: control means for controlling the storage of one digit of the binary coded output numeral information from said first register in said buffer register during at least more than one digit time.

Claim 18

A numeral output system for a register according to claim 15 wherein said control means includes a timing pulse generator and gate means.

Claim 19

A numeral output system for a register according to claim 9 wherein said first register comprises a plurality of digit stages each being connected in series together and having a four bit parallel configuration, and said first register has a circulating loop.

Claim 20

A numeral output system for a register comprising: a first register having a plurality of digit stages and a circulating loop for storing therein and circulating therethrough at least binary coded output numeral information; a second register having an input terminal which is connected to an output terminal of said first register for storing therein one digit of the binary coded output numeral information from said first register during at least more than one digit time, said second register being disposed outside of said circulating loop; control means for controlling the storage of one digit of the binary coded output numeral information from said first register in said second register during at least more than one digit time; and output means for visually displaying the binary coded output numeral information of said second register.

Claim 21

A numeral output system for a register comprising: a first register having a plurality of digit stages and a circulating loop for storing therein and circulating therethrough at least binary coded output numeral information; a second register having an input terminal which is connected to an output terminal of said first register for storing therein one digit of the binary coded output numeral information from said first register during at least more than one digit time, said second register being disposed outside of said circulating loop; control means for controlling the storage of one digit of the binary coded output numeral information from said first register in said second register during at least more than one digit time; and output means for visually displaying the binary coded output numeral information of said second register.

Claim 22

A numeral output system for a register according to claim 18 further comprising: means for detecting an insignificant zero in said first register while one digit of the binary coded numeral information from said first register is being stored in said second register.

Claim 23

A numeral output system for a register according to claim 18 wherein said first register comprises a plurality of digit stages, each being connected in series together and having a four bit parallel configuration.

Claim 24

A numeral output system for a register according to claim 18 wherein said control means includes a timing pulse generator and gate means.

Claim 25

A numeral output system for a register according to claim 18 wherein said output means comprises a multi-digit numeral display device.

Claim 26

A numeral output system for a register according to claim 18 wherein said output means comprises a printer.

Claim 27

A numeral output system for a register according to claim 19 wherein said insignificant zero detecting means develops a control signal for every digit, said control signal having a first signal level during which transferring of the output numeral information to said output means is inhibited and having a second signal level during which transferring of the output numeral information to said output means is permitted.

Claim 28

A numeral output system for a register comprising: a first register having a plurality of digit stages for storing therein at least binary coded numeral output information which is shifted from the upper significant digit thereof toward the lower significant digit and circulated therethrough; a second register for storing therein one digit of the binary coded numeral output information from said shift register; means for controlling the storage, in turn, of one digit of the binary coded output numeral information from said first register into said second register in accordance with a sequence of digit positions from the lower significant digit toward the upper significant digit and to store said one digit during at least more than one digit time; means for detecting an insignificant zero in turn from the lower significant digit of said first register, said insignificant zero detecting means including at least three flip-flops; and output means interconnected to said insignificant zero detecting means and said second register for visually displaying the binary coded output numeral information in said second register.

Claim 29

A numeral output system for a register comprising: a first register having a plurality of digit stages for storing therein at least binary coded numeral output information which is shifted from the upper significant digit thereof toward the lower significant digit and circulated therethrough; a second register for storing therein one digit of the binary coded numeral output information from said shift register; means for controlling the storage, in turn, of one digit of the binary coded output numeral information from said first register into said second register in accordance with a sequence of digit positions from the lower significant digit toward the upper significant digit and to store said one digit during at least more than one digit time; means for detecting an insignificant zero in turn from the lower significant digit of said first register, said insignificant zero detecting means including at least three flip-flops; and output means interconnected to said insignificant zero detecting means and said second register for visually displaying the binary coded output numeral information in said second register.

Claim 30

A numeral output system for a register according to claim 25 wherein said first register comprises a plurality of digit stages each being connected in series together and having a four bit parallel configuration.

Claim 31

A numeral output system for a register according to claim 25 wherein said output means comprises a multi-digit numeral display device.

Claim 32

A numeral output system for a register according to claim 25 wherein said output means comprises a printer.

Claim 33

A numeral output system for a register according to claim 25 wherein said control means comprises a timing pulse generator and gate means.