Patent US3955182A successfully refreshed from Google Patents.
US3955182A
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Transistorised memory cell and an integrated memory using such a cell
Assignee: Thales SA
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Filing: 1975-03-21
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Granted: 1976-05-04
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Expires: 1995-03-21
Abstract
Abstract A memory cell as required for use in the building of integrated memories, which contains bistable trigger stages formed by two transistors, with a high operational reliability, a low power consumption and an access time of less than 0.01 microseconds for a store of 64 elements, is provided. To this end, low-consumption field-effect transistors are chosen, obtained by the ion implantation of an N-type channel, in order, in each cell, to form, in addition to the two transistors of the trigger stage, a pair of transistors connected as amplifier-followers. The selection of a cell is effected by raising the potential on the word line connected to the sources of the transistors of the trigger stage.
Inventors
- 👤 Georges Bert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:13
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
70 words
A transistorised memory cell, comprising a first and a second field-effect transistors constituting a logic trigger stage of bistable design with two inputs/outputs and having their sources connected to one and the same word line, a third and a fourth field-effect transistors respectively connected as amplifier-followers, their gates being connected respectively to each of said inputs/outputs, and their sources being connected respectively to a first and a second write-in/read-out line.
Claim 2
Dependent Claim
70 words
A transistorised memory cell, comprising a first and a second field-effect transistors constituting a logic trigger stage of bistable design with two inputs/outputs and having their sources connected to one and the same word line, a third and a fourth field-effect transistors respectively connected as amplifier-followers, their gates being connected respectively to each of said inputs/outputs, and their sources being connected respectively to a first and a second write-in/read-out line.
Claim 3
Dependent Claim
28 words
A memory comprising pq cells (where p and q are whole numbers) as claimed in claim 1 said cells being formed on one and the same semi-conductor substrate.
Claim 4
Dependent Claim
68 words
A memory as claimed in claim 2, wherein said word lines are connected across a resistor to a first direct supply terminal also supplying the drains of the amplifier transistors of the differing elements, each of them being alternately earthed and isolated from earth through the medium of the channel of an address transistor of field-effect type, integrated into the same substrate as the rest of the memory.
Claim 5
Dependent Claim
68 words
A memory as claimed in claim 3, wherein the two write-in/read-out lines of each column of cells, are furthermore connected, across a resistive load, to a second supply terminal of opposite sign to the first, each of them being alternately earthed and insulated from earth through the medium of the channel of a transistor of field-effect type, integrated into the same substrate as the rest of the memory.
References Cited (Backward Citations)
US3668656A
Cited
US3633182A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-05-04 | 1979-11-03 | 1980-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-05-04 | 1983-11-03 | 1984-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-05-04 | 1987-11-03 | 1988-05-04 | $7700.00 | Window Closed / Lapsed |