Patent US3955099A successfully refreshed from Google Patents.
US3955099A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Diode controlled idle current injection
Assignee: Raytheon Co
•
Filing: 1974-03-11
•
Granted: 1976-05-04
•
Expires: 1994-03-11
Abstract
Abstract Diodes having a fast response time are used in an Emitter-Coupled Logic (ECL) current switch circuit to cause the injection of an idle current in each of the transistors of said switch. The injection of the idle current through these transistors causes them to operate at all times in an active region. When the transistors remain in the active operating region and are subjected to a switching transient, the parasitic capacitance associated with emitter base and collector base junctions are not charged and discharged to the same extent that they would be if the transistor was turned off completely. Moreover, if the transistors are held on, delay required for minority profile "buildup" in the base region is reduced and the current switch's propagation delay is reduced. When the fast response diodes are used to cause the injection of idle current in a cascode circuit, the overall transient response is greatly improved in both the lower and upper current switch sections; and there is a reduction of spurious output signals. Schottky diodes can be used in said circuit due to their fast response time. Alternatively large value resistors or current source transistors are used when diodes are not used.
Inventors
- 👤 James R. Gaskill, Jr.
- 👤 Don C. Devendorf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0866; H03K19/01; H03K19/013
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
321 words
In an ECL network having a lower current switching circuit and a first and second upper current switching circuit, each circuit comprising a pair of input transistors, whose emitters are connected together, each upper circuit having the bases of one of its input transistors connected to input signals, the bases of other two transistors of said upper circuits being connected to each other and to a bias voltage source, the emitters of said first upper circuit being connected to the collector of said first transistor of said lower circuit and the emitters of said second upper circuit being connected to the collector of said second transistor of said lower circuit, the base of said first transistor being connected to a level shifted input signal and the base of said second transistor of said lower circuit being connected to a bias voltage source, wherein the improvement comprises: a switch current source; a plurality of idle current sources; a plurality of fast response diodes, the anode of the first of said diodes being connected to the emitter of said first transistor of said lower circuit and to the first of said idle current sources and the cathode of said first diode being connected to the cathode of said second diode and to said switch current source, the anode of second diode being connected to the emitter of said second transistor of said lower circuit and to said second idle current source; said diodes either conduct current from said switch current source through said transistors or block said switch current flow and allow idle current from said idle current sources to flow through said transistors, keeping said transistors turned on, thereby reducing said circuit's propagation delay time and eliminating glytch output signals from said circuit; and said diodes also eliminate delay due to parasitic capacitance at the emitters of said transistors, thereby reducing the switching time of said transistors and the circuit's propagation time.
Claim 2
Dependent Claim
321 words
In an ECL network having a lower current switching circuit and a first and second upper current switching circuit, each circuit comprising a pair of input transistors, whose emitters are connected together, each upper circuit having the bases of one of its input transistors connected to input signals, the bases of other two transistors of said upper circuits being connected to each other and to a bias voltage source, the emitters of said first upper circuit being connected to the collector of said first transistor of said lower circuit and the emitters of said second upper circuit being connected to the collector of said second transistor of said lower circuit, the base of said first transistor being connected to a level shifted input signal and the base of said second transistor of said lower circuit being connected to a bias voltage source, wherein the improvement comprises: a switch current source; a plurality of idle current sources; a plurality of fast response diodes, the anode of the first of said diodes being connected to the emitter of said first transistor of said lower circuit and to the first of said idle current sources and the cathode of said first diode being connected to the cathode of said second diode and to said switch current source, the anode of second diode being connected to the emitter of said second transistor of said lower circuit and to said second idle current source; said diodes either conduct current from said switch current source through said transistors or block said switch current flow and allow idle current from said idle current sources to flow through said transistors, keeping said transistors turned on, thereby reducing said circuit's propagation delay time and eliminating glytch output signals from said circuit; and said diodes also eliminate delay due to parasitic capacitance at the emitters of said transistors, thereby reducing the switching time of said transistors and the circuit's propagation time.
Claim 3
Dependent Claim
14 words
In an ECL circuit as recited in claim 1, said diodes comprise Schottky diodes.
Claim 4
Dependent Claim
178 words
In an Emitter-Coupled Logic (ECL) cascode current switching circuit having a lower current switching circuit and a first and second upper current switching circuit, each circuit comprising a pair of input transistors, whose emitters are connected together, each upper circuit having the bases of one of its input transistors connected to input signals, the bases of the other two transistors of said upper circuits being connected to each other and to a bias voltage source, the emitters of said first upper circuit being connected to the collector of said first transistor of said lower circuit and the emitters of said second upper circuit being connected to the collector of said second transistor of said lower circuit, the base of said first transistor being connected to a level shifted input signal and the base of said second transistor of said lower circuit being connected to a bias voltage source, wherein the improvement comprises: means for injecting idle current into at least one of said upper current switch transistors, to reduce said circuit's propagation delay time and spurious output signals.
Claim 5
Dependent Claim
178 words
In an Emitter-Coupled Logic (ECL) cascode current switching circuit having a lower current switching circuit and a first and second upper current switching circuit, each circuit comprising a pair of input transistors, whose emitters are connected together, each upper circuit having the bases of one of its input transistors connected to input signals, the bases of the other two transistors of said upper circuits being connected to each other and to a bias voltage source, the emitters of said first upper circuit being connected to the collector of said first transistor of said lower circuit and the emitters of said second upper circuit being connected to the collector of said second transistor of said lower circuit, the base of said first transistor being connected to a level shifted input signal and the base of said second transistor of said lower circuit being connected to a bias voltage source, wherein the improvement comprises: means for injecting idle current into at least one of said upper current switch transistors, to reduce said circuit's propagation delay time and spurious output signals.
Claim 6
Dependent Claim
338 words
In an ECL network having a lower current switching circuit and a first and second upper current switching circuit, each circuit comprising a plurality of input transistors and a reference transistor, their emitters being connected, each upper circuit having the bases of one of its input transistors connected to input signals, the bases of the other two reference transistors of said upper circuits being connected to each other and to a bias voltage source, the emitters of said first upper circuit being connected to the collector of said first transistor of said lower circuit and the emitters of said second upper circuit being connected to the collector of said second transistor of said lower circuit, the base of said first transistor being connected to a plurality of level shifted input signals and the base of said second transistor of said lower circuit being connected to a bias voltage source the emitters of the lower current switching transistors being connected together and to the collector of a current source transistor, that current source transistor having its emitter connected through a resistor to a negative voltage source and its base to a diode reference circuit, wherein the improvement comprises: a first and second idle current source, each comprising a resistor; said first idle current source is connected between said emitters of said first upper circuit and any appropriate negative voltage source or constant voltage point within said circuit, for supplying idle current to said emitters in order to keep said transistors of said first upper circuit partially conducting at all times to reduce said network's switching time; said second idle current source is connected between said emitters of said second upper circuit and said negative voltage source for supplying idle current to said emitters in order to keep said transistors of said second circuit partially conducting at all times to reduce said network's switching time; a switch current source comprising a transistor and a resistor, which is connected between said emitters of said lower circuit and said negative voltage source.
Claim 7
Dependent Claim
338 words
In an ECL network having a lower current switching circuit and a first and second upper current switching circuit, each circuit comprising a plurality of input transistors and a reference transistor, their emitters being connected, each upper circuit having the bases of one of its input transistors connected to input signals, the bases of the other two reference transistors of said upper circuits being connected to each other and to a bias voltage source, the emitters of said first upper circuit being connected to the collector of said first transistor of said lower circuit and the emitters of said second upper circuit being connected to the collector of said second transistor of said lower circuit, the base of said first transistor being connected to a plurality of level shifted input signals and the base of said second transistor of said lower circuit being connected to a bias voltage source the emitters of the lower current switching transistors being connected together and to the collector of a current source transistor, that current source transistor having its emitter connected through a resistor to a negative voltage source and its base to a diode reference circuit, wherein the improvement comprises: a first and second idle current source, each comprising a resistor; said first idle current source is connected between said emitters of said first upper circuit and any appropriate negative voltage source or constant voltage point within said circuit, for supplying idle current to said emitters in order to keep said transistors of said first upper circuit partially conducting at all times to reduce said network's switching time; said second idle current source is connected between said emitters of said second upper circuit and said negative voltage source for supplying idle current to said emitters in order to keep said transistors of said second circuit partially conducting at all times to reduce said network's switching time; a switch current source comprising a transistor and a resistor, which is connected between said emitters of said lower circuit and said negative voltage source.
Claim 8
Dependent Claim
28 words
In an ECL circuit as recited in claim 3, wherein said means comprises a resistor connected between the emitters of said upper circuits and said negative voltage source.
Claim 9
Dependent Claim
68 words
In an ECL circuit as recited in claim 4 wherein each idle current source comprises a transistor with a resistor connected between its emitter and said negative supply voltage and the collector of each current source transistor connected respectively to the emitters of one of said upper circuits, the bases of said current source transistors being connected in common to the base of the main current source transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-05-04 | 1979-11-03 | 1980-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-05-04 | 1983-11-03 | 1984-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-05-04 | 1987-11-03 | 1988-05-04 | $7700.00 | Window Closed / Lapsed |