US3952289A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controller for linking a typewriter console to a processor unit
Assignee: Unisys Corp
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Filing: 1975-02-03
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Granted: 1976-04-20
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Expires: 1995-02-03
Abstract
Abstract A controller implemented on a single LSI MOS chip is described for linking a typewriter console to a processor unit. The controller comprises a FIFO (First-In-First-Out) buffer for storing the keyboard data characters read-out from the console. The buffer includes a flag for each stage, each flag being controlled to assume a first condition when its respective stage is occupied by a character, and a second condition when it is vacant of a character. The keyboard data characters are inputted into the first stage by strobe pulses, and are continuously shifted by high-speed clock pulses to the highest stage of the buffer whose flag is in the stage-vacant condition, the characters being read-out from the last stage. The buffer includes means for preventing the entry of a new character, and also for providing an indication of an "Overflow" condition, whenever a strobe pulse is received by the buffer while the first-stage flag of the buffer is in the stage-occupied condition.
Inventors
- 👤 Jacques A. Baligant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:57
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/01; G06F3/02; G06F3/0227
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
249 words
A controller for linking a typewriter console to processor unit, the typewriter console having a keyboard including means for reading-out the keyboard data characters, said controller comprising: a storage buffer having a plurality of stages; a plurality of flags, one for each stage of the buffer; means for causing each flag to assume a first condition when its respective stage is occupied by a character, and a second condition when its respective stage is vacant of a character; means for supplying a series of strobe pulses and a series of clock pulses, the rate of clock pulses being many times faster than the rate of strobe pulses; means controlled by said strobe pulses for serially reading each keyboard data character into the first stage of the buffer to store same therein and to cause its respective flag to assume said first, stage-occupied, condition; means controlled by said clock pulses for continuously shifting the data character stored in the buffer towards the last stage of the buffer, to be stored in the highest stage of the buffer whose flag is in said second, stage-vacant, condition; means for serially reading out to the processor unit the stored keyboard data characters from the last stage of the buffer; and means preventing the entry of a character into the buffer and for providing an indication of an "0verflow" condition whenever a strobe pulse is received by the buffer while the flag of the first stage of the buffer is in said stage-occupied condition.
Claim 2
Dependent Claim
249 words
A controller for linking a typewriter console to processor unit, the typewriter console having a keyboard including means for reading-out the keyboard data characters, said controller comprising: a storage buffer having a plurality of stages; a plurality of flags, one for each stage of the buffer; means for causing each flag to assume a first condition when its respective stage is occupied by a character, and a second condition when its respective stage is vacant of a character; means for supplying a series of strobe pulses and a series of clock pulses, the rate of clock pulses being many times faster than the rate of strobe pulses; means controlled by said strobe pulses for serially reading each keyboard data character into the first stage of the buffer to store same therein and to cause its respective flag to assume said first, stage-occupied, condition; means controlled by said clock pulses for continuously shifting the data character stored in the buffer towards the last stage of the buffer, to be stored in the highest stage of the buffer whose flag is in said second, stage-vacant, condition; means for serially reading out to the processor unit the stored keyboard data characters from the last stage of the buffer; and means preventing the entry of a character into the buffer and for providing an indication of an "0verflow" condition whenever a strobe pulse is received by the buffer while the flag of the first stage of the buffer is in said stage-occupied condition.
Claim 3
Dependent Claim
36 words
A controller according to claim 1, wherein each strobe pulse is of substantially larger duration than that of each complete clock cycle for shifting a character from the first to the last stage of the buffer.
Claim 4
Dependent Claim
54 words
A controller according to claim 1, further including means sensing the condition of the flag in the highest stage of the buffer, said latter means enabling the read-out from the buffer when said flag is in the stage-occupied condition, and terminating the read-out from the buffer when said flag is in the stage-vacant condition.
Claim 5
Dependent Claim
45 words
A controller according to claim 3, wherein said last-mentioned means, when the highest stage flag is in the stage-vacant condition, causes the controller automatically to inform the processor unit as to whether the typewriter console is in an "Overflow" condition with respect to said buffer.
Claim 6
Dependent Claim
39 words
A controller according to claim 1, further including decoder means for decoding a "Keyboard-Select" instruction from the processor unit enabling the read-in with a strobe pulse of a character from the keyboard into the first stage of the buffer.
Claim 7
Dependent Claim
41 words
A controller according to claim 5, wherein said decoder means further includes means for decoding a "Read" instruction from the processor unit to effect the serial read-out of the characters from the last stage of the buffer to the central facility.
Claim 8
Dependent Claim
47 words
A controller according to claim 1 for a typewriter console having a plurality of indicators, wherein said controller further includes means for energizing at least one of the indicators to indicate the "Overflow" condition, and means for causing said "Overflow" indicator to "blink" at a preselected frequency.
Claim 9
Dependent Claim
81 words
A controller according to claim 1 for a typewriter console having a plurality of indicators, wherein the controller further includes: a plurality of registers for said indicators; decoder means for decoding an "Enabling" instruction from the processor unit enabling a selected register and for decoding a subsequent "Write" instruction from the processor unit to effect a transfer of indicator data from the processor unit to the enabled register; and means for reading-out the data from said enabled register to the indicators.
Claim 10
Dependent Claim
26 words
A controller according to claim 8, wherein said last-named means includes a multiplexer for scanning the indicator registers and for reading-out their contents to the indicators.
Claim 11
Dependent Claim
55 words
A controller according to claim 9, further including multiplexer control means for selectively operating said multiplexer according to a first mode wherein the contents of only one register are read-out to the indicators, a second mode wherein only certain ones of said registers are scanned, or a third mode wherein all said registers are scanned.
Claim 12
Dependent Claim
43 words
A controller according to claim 10, wherein the multiplexer-control means includes means for causing the multiplexer to scan at a faster scanning rate and with shorter sampling periods when operated according to said second mode than when operated according to said third mode.
Claim 13
Dependent Claim
26 words
A controller according to claim 10, wherein said multiplexer-control means includes flags presettable by instructions from the processor unit in accordance with the selected multiplexer mode.
Claim 14
Dependent Claim
25 words
A controller according to claim 12, further including additional flags presettable by instructions from the processor unit for selectively blinking certain ones of the indicators.
Claim 15
Dependent Claim
39 words
A controller according to claim 13, further including a divider circuit receiving a single-frequency reference signal and producing therefrom a plurality of different-frequency timing signals controlling the multiplexing of the indicator registers, and the blinking of the selected indicators.
Claim 16
Dependent Claim
46 words
A controller according to claim 1 for a typewriter console having a plurality of switches, wherein said controller includes decoder means for decoding an "Enabling" instruction and a subsequent "Read" instruction from the processor unit to effect a read-out of the switches to the processor unit.
Claim 17
Dependent Claim
20 words
A controller according to claim 1, wherein the circuitry of the controller is formed on a single, LSI MOS chip.
Claim 18
Dependent Claim
27 words
A data processing system including a processor unit, a typewriter console, and a controller in accordance with claim 1 linking the typewriter console to the processor unit.
Claim 19
Dependent Claim
244 words
A plural-stage buffer for temporarily storing a plurality of data characters, comprising: a plurality of flags, one for each stage of the buffer; means for causing each flag to assume a first condition when its respective stage is occupied by a character, and a second condition when its respective stage is vacant of a character; means for supplying a series of strobe pulse and a series of clock pulses, the rate of clock pulses being many times faster than the rate of strobe pulses; means controlled by said strobe pulses for serially reading each data character into the first stage of the buffer to store same therein, and to cause its respective flag to assume said first, stage-occupied, condition; means controlled by said clock pulses for continuously shifting each data character stored in the buffer towards the last stage of the buffer, to be stored in the highest stage of the buffer whose flag is in said second, stage-vacant condition; means for serially reading out the data characters from the last stage of the buffer; means providing an indication whenever a character is supplied to the buffer while the flag of its first stage is in said stage-occupied condition; and means preventing the entry of a character into the buffer, and also for providing an indication of an "Overflow" condition, whenever a strobe pulse is received by the buffer while the flag of the first stage of the buffer is in said stage-occupied condition.
Claim 20
Dependent Claim
244 words
A plural-stage buffer for temporarily storing a plurality of data characters, comprising: a plurality of flags, one for each stage of the buffer; means for causing each flag to assume a first condition when its respective stage is occupied by a character, and a second condition when its respective stage is vacant of a character; means for supplying a series of strobe pulse and a series of clock pulses, the rate of clock pulses being many times faster than the rate of strobe pulses; means controlled by said strobe pulses for serially reading each data character into the first stage of the buffer to store same therein, and to cause its respective flag to assume said first, stage-occupied, condition; means controlled by said clock pulses for continuously shifting each data character stored in the buffer towards the last stage of the buffer, to be stored in the highest stage of the buffer whose flag is in said second, stage-vacant condition; means for serially reading out the data characters from the last stage of the buffer; means providing an indication whenever a character is supplied to the buffer while the flag of its first stage is in said stage-occupied condition; and means preventing the entry of a character into the buffer, and also for providing an indication of an "Overflow" condition, whenever a strobe pulse is received by the buffer while the flag of the first stage of the buffer is in said stage-occupied condition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-04-20 | 1979-10-20 | 1980-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-04-20 | 1983-10-20 | 1984-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-04-20 | 1987-10-20 | 1988-04-20 | $7700.00 | Window Closed / Lapsed |