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US3950940A Expired / Lapsed US ⏱️ 0.0 years remaining

Electronic timepiece

Assignee: Suwa Seikosha KK
•
Filing: 1974-08-02
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Granted: 1976-04-20
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Expires: 1994-08-02
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Abstract

Abstract An electronic timepiece having the electronic circuitry formed as a single monolithically integrated circuit chip is provided, a first portion of the circuitry being actuated by a first potential and a second portion of the circuitry being actuated by a second potential higher than said first. The circuit chip includes complementary coupled MOS transistors, the first and second circuit portions operating respectively at first and second logic levels. An interface is provided intermediate said first and second circuit portions, the interface being adapted to effect an interfacing of said logic levels, and an electrical insulation of said first and second circuit portions.

Inventors

  • 👤 Izuhiko Nishimura
  • 👤 Satoshi Fushimi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 19:53
CPC Classifications
G; G04; G04G; G04G99/00; H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 114 words
In an electronic timepiece having the operative circuits thereof monolithically integrated into a single circuit chip, said circuit chip including complementary coupled MOS transistors, the improvement comprising a circuit chip including a first complementary coupled MOS transistor operative circuit portion adapted to be energized by a first potential to thereby operate at a first logic level and a second complementary coupled MOS transistor circuit portion energized at a second potential higher than said first potential to operate at a second logic level, and interface means between said first and second complementary coupled MOS transistor portions, said interface means interfacing said first and second logic levels, and electrically insulating said first and second circuit portions.
Claim 2
Dependent Claim 114 words
In an electronic timepiece having the operative circuits thereof monolithically integrated into a single circuit chip, said circuit chip including complementary coupled MOS transistors, the improvement comprising a circuit chip including a first complementary coupled MOS transistor operative circuit portion adapted to be energized by a first potential to thereby operate at a first logic level and a second complementary coupled MOS transistor circuit portion energized at a second potential higher than said first potential to operate at a second logic level, and interface means between said first and second complementary coupled MOS transistor portions, said interface means interfacing said first and second logic levels, and electrically insulating said first and second circuit portions.
Claim 3
Dependent Claim 46 words
An electronic timepiece as claimed in claim 1, wherein said first circuit portion defines a quartz crystal oscillator circuit for producing a high frequency time standard signal and a divider circuit for producing low frequency timekeeping signals in response to said high frequency time standard signal.
Claim 4
Dependent Claim 25 words
An electronic timepiece as claimed in claim 1, wherein said second circuit portion defines a driving circuit for supplying driving signals to a digital display.
Claim 5
Dependent Claim 25 words
An electronic timepiece as claimed in claim 2, wherein said second circuit portion defines a driving circuit for supplying driving signals to a digital display.
Claim 6
Dependent Claim 24 words
An electronic timepiece as claimed in claim 4, wherein said first potential equals about 1.5 volts and said second potential is a higher voltage.
Claim 7
Dependent Claim 21 words
An electronic timepiece as claimed in claim 5, wherein said second potential higher than said first potential is about 3.0 volts.

References Cited (Backward Citations)

US3701249A Cited
US3675043A Cited
US3820108A Cited
US3860830A Cited
US3757510A Cited
US3803827A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-04-20 1979-10-20 1980-04-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-04-20 1983-10-20 1984-04-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-04-20 1987-10-20 1988-04-20 $7700.00 Window Closed / Lapsed

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