Self-clocking NRZ recording and reproduction system

Claim 2

In a data storage system of the type wherein data is stored in a bulk medium according to a binary code in which opposite bit values are represented in bit cells by respective levels and wherein the sync transition occurs every n data bit cells: a readout system comprising clock means responsive to the occurrence of a sync transition for generating a sequence of timing signals representing the position in time of successive data cells being read, means for reading the bit values in the successive bit cells, means for counting the successive bit cells to identify each occurrence of n data bit cells, and compensation means responsive to particular patterns of the level transitions associated with the data cells preceding and following each identified sync transition of n data bit cells for adjusting the time relationship between the sync transition and said sequence of reading the bit values in the successive bit cells in accordance with such particular patterns to compensate for shifting of said sync transition as read from said medium by said readout system.

Claim 3

Apparatus as set forth in claim 1 wherein means are included for comparing the characteristics of the signals read out by the readout system at the bit cells immediately preceding and immediately following each sync transition of n data bit cells, and means are responsive to the signals from the comparing means, in accordance with each comparison, for adjusting the time for reading the data bits after the sync transition of n data bit cells.

Claim 4

In a magnetic data storage system of the type wherein data is stored in a bulk medium according to a binary code in which opposite bit values are represented in bit cells by respective flux levels and wherein the sync flux transition occurs every n data bit cells: a readout system comprising clock means responsive to the occurrence of a sync transition for generating a sequence of time signals representing the position in time of successive data cells being read, and compensation means responsive to the flux level transitions associated with the data cells preceding and following the sync transition for adjusting the time relationship between the sync transition and said sequence to compensate for shifting of said sync transition in said medium, the compensation means comprising a plurality of delay means having inputs connected to receive said sync flux transitions and outputs connected to said clock means and representing respective time delays, decoder means responsive to data and sync transitions for producing output signals representing sync transition shifts, and logic means responsive to the output signal from said decoder means to operatively connect one of said plurality of delay means in operative input relationship with said clock means to select a time delay for compensation of the sync transition shift.

Claim 5

In a magnetic data storage system of the type wherein data is stored in a bulk medium according to a binary code in which opposite bit values are represented in bit cells by respective flux levels and wherein the sync flux transition occurs every n data bit cells: a readout system comprising clock means responsive to the occurrence of a sync transition for generating a sequence of time signals representing the position in time of successive data cells being read, and compensation means responsive to the flux level transitions associated with the data cells preceding and following the sync transition for adjusting the time relationship between the sync transition and said sequence to compensate for shifting of said sync transition in said medium, the compensation means comprising a plurality of delay means having inputs connected to receive said sync flux transitions and outputs connected to said clock means and representing respective time delays, decoder means responsive to data and sync transitions for producing output signals representing sync transition shifts, and logic means responsive to the output signal from said decoder means to operatively connect one of said plurality of delay means in operative input relationship with said clock means to select a time delay for compensation of the sync transition shift.

Claim 6

Apparatus as defined in claim 3 wherein the delay means include a first delay of median time, a second delay of a time longer than said median, and a third delay of a time shorter than said median.

Claim 7

Apparatus as defined in claim 4 wherein said decoder means includes inputs responsive only to the sync transition and the data transitions corresponding to the data cells immediately preceding and following the sync transition.

Claim 8

Apparatus as defined in claim 4 including means for proportionately varying all of the delay times of said first, second, and third delays according to memory medium displacement rate.

Claim 9

Apparatus as defined in claim 5 wherein said clock means includes a first oscillator, and input means for resetting the oscillator, said delay means being connected to said input means for resetting the oscillator after each of said sync transitions.

Claim 10

Apparatus as defined in claim 7 wherein said clock means includes a second oscillator, an output gate, and means for alternatingly connecting the first and second oscillators to the output gate.

Claim 11

In combination for use with apparatus for storing bit values in bit cells wherein changes in bit values are represented by changes in voltage levels and wherein a sync transition is provided every n bit cells, first means for reading the voltage levels to reproduce the bit values, second means for counting the bit cells to produce a signal indicating each sync transition of n bit cells, third means responsive to the operation of the first and second means for producing clock signals to synchronize the operation of the first and second means, and fourth means responsive to the bit values read by the first means in the bit cells immediately preceding and immediately following each signal produced by the second means for adjusting the time for the production by the third means of the clock signals in accordance with the relative bit values in such immediately preceding and immediately following bit cells.

Claim 12

In combination for use with apparatus for storing bit values in bit cells wherein changes in bit values are represented by changes in voltage levels and wherein a sync transition is provided every n bit cells, first means for reading the voltage levels to reproduce the bit values, second means for counting the bit cells to produce a signal indicating each sync transition of n bit cells, third means responsive to the operation of the first and second means for producing clock signals to synchronize the operation of the first and second means, and fourth means responsive to the bit values read by the first means in the bit cells immediately preceding and immediately following each signal produced by the second means for adjusting the time for the production by the third means of the clock signals in accordance with the relative bit values in such immediately preceding and immediately following bit cells.

Claim 13

In the combination set forth in claim 9, the fourth means including a decoder for adjusting the time for the production by the third means for the clock signals when the bit value for the immediately preceding bit cell is different from the bit value for the immediately following bit cell.

Claim 14

In the combination set forth in claim 10, the fourth means including logical circuitry for providing for an increase in the delay for the production by the third means of the clock signals when the first means reads a change in the voltage level in the immediately following bit cell.

Claim 15

In the combination set forth in claim 10, the fourth means including logical circuitry for providing for a decrease in the delay for the production by the third means of the clock signals when the first means reads a change in the voltage level in the immediately preceding bit cell.

Claim 16

In the combination set forth in claim 9, means for providing for an adjusting in the time for reading the bit values for the bit cells and means responsive to a comparision between the bit values for the bit cells immediately preceding and immediately following each sync transition of n bit cells for energizing the adjusting means to adjust the time for reading the bit values for the data cells.

Claim 17

In the combination set forth in claim 13, the clock means including oscillator means and the fourth means including means responsive to the energizing of the adjusting means for resetting the oscillator means after each of the sync transitions in accordance with the adjustments provided in the adjusting means.