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US3947829A
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Logical circuit apparatus
Assignee: Toshiba Corp
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Filing: 1974-07-22
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Granted: 1976-03-30
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Expires: 1994-07-22
Abstract
Abstract A plurality of logical control circuits each having a storage or delay function are driven by a writing-in clock pulse φ1 and a reading-out clock pulse φ2 supplied in common thereto and receiving output signals from a Read Only Memory constructed in the form of a matrix. This Read Only Memory is constituted by a plurality of logical gate circuits each supplied with a plurality of prescribed signals of a pulse signal group having a plurality of input signals I1, I2, . . . In and control pulse signals T8, D4, A and B different in frequency from the clock pulses φ1 and φ2. The logical control circuit includes a first logical gate supplied with a feed back signal from the logical control circuit and a prescribed control pulse signal and a second logical gate supplied with an output signal generated from the corresponding logical gate circuit of the Read Only Memory in accordance with the prescribed control pulse signal and prescribed input signals and with an output signal from the first logical gate the output of the second logical gate is delayed in response to clock pulses φ1 and φ2 and then is generated as an output signal from the logical control circuit.
Inventors
- 👤 Yasoji Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:44
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
185 words
A logical circuit apparatus comprising a plurality of logical control circuits each having either a delay circuit or a storage circuit driven by a writing-in clock pulse φ1 and a reading-out clock pulse φ2 supplied thereto; a logical gate circuit supplied with a signal group including a plurality of input signals and a plurality of control pulse signals each having a frequency different from that of said clock pulses φ1 and φ2 and constituted by a plurality of main logical gates each supplied with at least one input signal of said signal group and connected correspondingly to each of said logical control circuits and a plurality of auxiliary logical gates each supplied with at least one of said control pulse signals; and a plurality of logical control gate circuits respectively included in prescribed ones of said logical control circuits and connected correspondingly to each of said auxiliary logical gates, for making a logical control of an output from the corresponding logical gates in accordance with an output from a corresponding one of said auxiliary logical gates and a feedback signal from said logical control circuit.
Claim 2
Dependent Claim
185 words
A logical circuit apparatus comprising a plurality of logical control circuits each having either a delay circuit or a storage circuit driven by a writing-in clock pulse φ1 and a reading-out clock pulse φ2 supplied thereto; a logical gate circuit supplied with a signal group including a plurality of input signals and a plurality of control pulse signals each having a frequency different from that of said clock pulses φ1 and φ2 and constituted by a plurality of main logical gates each supplied with at least one input signal of said signal group and connected correspondingly to each of said logical control circuits and a plurality of auxiliary logical gates each supplied with at least one of said control pulse signals; and a plurality of logical control gate circuits respectively included in prescribed ones of said logical control circuits and connected correspondingly to each of said auxiliary logical gates, for making a logical control of an output from the corresponding logical gates in accordance with an output from a corresponding one of said auxiliary logical gates and a feedback signal from said logical control circuit.
Claim 3
Dependent Claim
77 words
A logical circuit apparatus according to claim 1 wherein at least one of said logical control gate circuits is constituted by an OR gate supplied with an output from said auxiliary logical gate and a feedback signal from said logical circuit and an AND gate supplied with an output from said OR gate and an output from said logical gate circuit to supply its output to said either one of the delay circuit and the storage circuit.
Claim 4
Dependent Claim
77 words
A logical circuit apparatus according to claim 1 wherein at least one of said logical control gate circuits is constituted by an AND gate supplied with an output from said auxiliary logical gate and a feedback signal from said logical circuit and an OR gate supplied with an output from said AND gate and an output from said logical gate circuit to supply its output to said either one of the delay circuit and the storage circuit.
Claim 5
Dependent Claim
35 words
A logical circuit apparatus according to claim 1 wherein said logical gate circuit is constituted by a Read Only Memory constituted by MOS transistors having a prescribed channel type in the form of a matrix.
Claim 6
Dependent Claim
33 words
A logical circuit apparatus according to claim 4 wherein said logical control circuit is constituted by MOS transistors having a channel type different from that of MOS transistors constituting said logical gate circuit.
Claim 7
Dependent Claim
26 words
A logical circuit apparatus according to claim 1 wherein the main and auxiliary logical gates included in said logical gate circuit are constituted by NAND gates.
Claim 8
Dependent Claim
163 words
A logical circuit apparatus comprising a plurality of logical control circuits each having either a delay circuit or a storage circuit driven by a writing-in clock pulse φ1 and a reading-out clock pulse φ2 supplied thereto, a logical gate circuit supplied with a plurality of input signals and constituted by a plurality of main logical gates each supplied with at least one of said input signals and a plurality of auxiliary logical gates each supplied with at least prescribed one of said input signals which contain a frequency component different from that of said clock pulses φ1 and φ2, and a plurality of logical control gate circuits respectively included in prescribed ones of said logical control circuits and connected correspondingly to each of said auxiliary logical gates, for making a logical control of an output from the corresponding logical gate in accordance with an output from a corresponding one of said auxiliary logical gates and a feedback signal from said logical control circuit.
Claim 9
Dependent Claim
163 words
A logical circuit apparatus comprising a plurality of logical control circuits each having either a delay circuit or a storage circuit driven by a writing-in clock pulse φ1 and a reading-out clock pulse φ2 supplied thereto, a logical gate circuit supplied with a plurality of input signals and constituted by a plurality of main logical gates each supplied with at least one of said input signals and a plurality of auxiliary logical gates each supplied with at least prescribed one of said input signals which contain a frequency component different from that of said clock pulses φ1 and φ2, and a plurality of logical control gate circuits respectively included in prescribed ones of said logical control circuits and connected correspondingly to each of said auxiliary logical gates, for making a logical control of an output from the corresponding logical gate in accordance with an output from a corresponding one of said auxiliary logical gates and a feedback signal from said logical control circuit.
References Cited (Backward Citations)
US3763480A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-30 | 1979-09-29 | 1980-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-30 | 1983-09-29 | 1984-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-30 | 1987-09-29 | 1988-03-30 | $7700.00 | Window Closed / Lapsed |