Patent US3947823A successfully refreshed from Google Patents.
US3947823A
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Means for coordinating asynchronous main store accesses in a multiprocessing system using virtual storage
Assignee: International Business Machines Corp
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Filing: 1973-12-26
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Granted: 1976-03-30
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Expires: 1993-12-26
Abstract
Abstract A unique control circuit that maintains the addressability to an invalidated page frame until execution is completed for all current instructions in all CPUs of a multiprocessing system which uses demand-paging and virtual addressing. A support method is also disclosed which provides an asynchronous sequence of operations for each CPU in the multiprocessing system to maintain the page in the invalidated page frame available to all CPUs and until their current instruction execution is completed. The last CPU to complete its execution moves the page, if modified, out of the page frame.
Inventors
- 👤 Andris Padegs
- 👤 Ronald Morton Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:32
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036; G06F12/14; G06F12/1416; G06F12/145
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
414 words
Apparatus for maintaining operand addressability to a page frame in a main store for current instructions in CPUs of a multiprocessing system using virtual storage addressing and demand-paging interruptions, in which each CPU has a virtual address register and an address translation means which provides main store addresses correspondng to virtual storage addresses received from the CPUs for addressing and accessing operands in a page within a page frame; and each CPU having lines for electrically signalling the CPU's requirements including a plurality of operand request lines, and an end operation line, apparatus in each CPU comprising a plurality of pairs of address availability registers, a plurality of availability control triggers respectively provided for the address availability registers, means for connecting a reset input of each control trigger to the end operation line, in order to reset the control triggers with an electric current provided on the end operation line to signal the end of execution for the current instruction, means for gating into a selected one of the availability registers a main store address provided by the address translation means, the virtual address register containing a page component with a low-order bit position, true and inverted output lines provided from the low-order bit position, the output of the virtual address register being connected to the input of the address translation means, a main store address register receiving the output of the translation means, a displacement component of the virtual address register being connected to a displacement component of the main store address register, a plurality of pairs of AND circuits, in which both AND circuits in each pair have inputs connected to a respective one of said plurality of operand request lines, one AND circuit in each pair also having an input connected to the true output line and the other AND circuit in the same pair also having an input connected to the inverted output line, and means for connecting the output of each AND circuit to a gating means at an input of a respective one of said address availability registers while the respective control trigger is in a reset state, means for connecting a set input of a respective one of said availability control triggers to the output of a respective one of the AND circuits, second gating means respectively connecting outputs of said availability registers to a main store address register, and the second gating means having an input conditioned by the set state of an associated control trigger.
Claim 2
Dependent Claim
414 words
Apparatus for maintaining operand addressability to a page frame in a main store for current instructions in CPUs of a multiprocessing system using virtual storage addressing and demand-paging interruptions, in which each CPU has a virtual address register and an address translation means which provides main store addresses correspondng to virtual storage addresses received from the CPUs for addressing and accessing operands in a page within a page frame; and each CPU having lines for electrically signalling the CPU's requirements including a plurality of operand request lines, and an end operation line, apparatus in each CPU comprising a plurality of pairs of address availability registers, a plurality of availability control triggers respectively provided for the address availability registers, means for connecting a reset input of each control trigger to the end operation line, in order to reset the control triggers with an electric current provided on the end operation line to signal the end of execution for the current instruction, means for gating into a selected one of the availability registers a main store address provided by the address translation means, the virtual address register containing a page component with a low-order bit position, true and inverted output lines provided from the low-order bit position, the output of the virtual address register being connected to the input of the address translation means, a main store address register receiving the output of the translation means, a displacement component of the virtual address register being connected to a displacement component of the main store address register, a plurality of pairs of AND circuits, in which both AND circuits in each pair have inputs connected to a respective one of said plurality of operand request lines, one AND circuit in each pair also having an input connected to the true output line and the other AND circuit in the same pair also having an input connected to the inverted output line, and means for connecting the output of each AND circuit to a gating means at an input of a respective one of said address availability registers while the respective control trigger is in a reset state, means for connecting a set input of a respective one of said availability control triggers to the output of a respective one of the AND circuits, second gating means respectively connecting outputs of said availability registers to a main store address register, and the second gating means having an input conditioned by the set state of an associated control trigger.
Claim 3
Dependent Claim
73 words
Apparatus as defined in claim 1 in which each CPU also has a non-operand request line, said apparatus also including a gating circuit connecting a page frame address output of said address translation means to the main store address register, and said gating circuit having an input conditioned by a non-operand signal current level on said non-operand request line, whereby said gating circuit permits the non-operand addresses to bypass the address availability registers.
Claim 4
Dependent Claim
312 words
Apparatus for maintaining operand addressability to one or more page frames in a shared main store for current instructions in CPUs of a multiprocessing system after invalidation of a page frame, in which each CPU has a virtual address register and an address translation means which provides main store addresses corresponding to virtual storage addresses received from the CPUs for accessing operands in page frames; and each CPU contains a plurality of operand request lines, and an end operation line, apparatus in each CPU comprising a plurality of address availability registers, a plurality of availability control triggers respectively provided with the address availability registers, means for connecting a reset input of each control trigger to the end operation line, in order to reset the control triggers when an instruction end current level is provided on the end operation line, means for gating into a selected one of the availability registers a page frame address being provided by the address translation means, the virtual address register containing a page component with a low-order bit position, true and inverted output lines provided from the low-order bit position, the output of the virtual address register being connected to an input of the address translation means, a plurality of AND circuits respectively associated with said address availability registers, in which each AND circuit has an input connected to one of said plurality of operand request lines, each AND circuit also having an input connected to the true or inverted output line for said low-order bit position, means for respectively connecting set inputs of said availability control triggers to output signal lines of the AND circuits, and plural gating means having inputs conditioned by a set output of a respective one of said control triggers, said gating means respectively connecting outputs of said address availability registers to a page frame input of a main store address register.
Claim 5
Dependent Claim
312 words
Apparatus for maintaining operand addressability to one or more page frames in a shared main store for current instructions in CPUs of a multiprocessing system after invalidation of a page frame, in which each CPU has a virtual address register and an address translation means which provides main store addresses corresponding to virtual storage addresses received from the CPUs for accessing operands in page frames; and each CPU contains a plurality of operand request lines, and an end operation line, apparatus in each CPU comprising a plurality of address availability registers, a plurality of availability control triggers respectively provided with the address availability registers, means for connecting a reset input of each control trigger to the end operation line, in order to reset the control triggers when an instruction end current level is provided on the end operation line, means for gating into a selected one of the availability registers a page frame address being provided by the address translation means, the virtual address register containing a page component with a low-order bit position, true and inverted output lines provided from the low-order bit position, the output of the virtual address register being connected to an input of the address translation means, a plurality of AND circuits respectively associated with said address availability registers, in which each AND circuit has an input connected to one of said plurality of operand request lines, each AND circuit also having an input connected to the true or inverted output line for said low-order bit position, means for respectively connecting set inputs of said availability control triggers to output signal lines of the AND circuits, and plural gating means having inputs conditioned by a set output of a respective one of said control triggers, said gating means respectively connecting outputs of said address availability registers to a page frame input of a main store address register.
Claim 6
Dependent Claim
356 words
In a multiprocessing system having a plurality of CPUs requiring operand addressability to page frames in a shared main store for executing current instructions of the CPUs, in which each CPU has a virtual address register and an address translation means which provides main store addresses for accessing operands in page frames; and each CPU contains a plurality of operand request lines, and an end operation line, each CPU in the system including a plurality of address availability registers capable of storing page frame addresses, a plurality of availability control triggers respectively provided with the address availability registers, means for connecting a reset input of each control trigger to the end operation line, in order to reset the control triggers when a signal is provided on the end operation line indicating an end of execution for the current instruction of the CPU, means for gating into a selected one of the availability registers a page frame address provided by the address translation means, the virtual address register containing a page component with a low-order part, respective tate output lines provided from the low-order part, the output of the virtual address register being connected to an input of the address translation means, a plurality of groups of AND circuits, each AND circuit being associated with a different one of said address availability registers, in which each AND circuit in a group has an input connected to a respective one of said plurality of operand request lines, each AND circuit in each group also has an input connected to a different one of the respective state output lines, means for connecting a set input of a respective one of said availability control triggers to an output signal line from an associated one of the AND circuits, plural gating means respectively having inputs conditioned by a set output of a respective one of said control triggers to respectively connect outputs of said address availability registers to a page frame input of a main store address register, whereby operand accessing by current instructions uses the page frame addresses provided to the main store address register by said address availability registers.
Claim 7
Dependent Claim
356 words
In a multiprocessing system having a plurality of CPUs requiring operand addressability to page frames in a shared main store for executing current instructions of the CPUs, in which each CPU has a virtual address register and an address translation means which provides main store addresses for accessing operands in page frames; and each CPU contains a plurality of operand request lines, and an end operation line, each CPU in the system including a plurality of address availability registers capable of storing page frame addresses, a plurality of availability control triggers respectively provided with the address availability registers, means for connecting a reset input of each control trigger to the end operation line, in order to reset the control triggers when a signal is provided on the end operation line indicating an end of execution for the current instruction of the CPU, means for gating into a selected one of the availability registers a page frame address provided by the address translation means, the virtual address register containing a page component with a low-order part, respective tate output lines provided from the low-order part, the output of the virtual address register being connected to an input of the address translation means, a plurality of groups of AND circuits, each AND circuit being associated with a different one of said address availability registers, in which each AND circuit in a group has an input connected to a respective one of said plurality of operand request lines, each AND circuit in each group also has an input connected to a different one of the respective state output lines, means for connecting a set input of a respective one of said availability control triggers to an output signal line from an associated one of the AND circuits, plural gating means respectively having inputs conditioned by a set output of a respective one of said control triggers to respectively connect outputs of said address availability registers to a page frame input of a main store address register, whereby operand accessing by current instructions uses the page frame addresses provided to the main store address register by said address availability registers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-30 | 1979-09-29 | 1980-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-30 | 1983-09-29 | 1984-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-30 | 1987-09-29 | 1988-03-30 | $7700.00 | Window Closed / Lapsed |