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US3947697A
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Synchronizing circuit including two flip-flops and circuit means to protect a synchronized signal from an unstable state of the flip-flops
Assignee: Alcatel Lucent NV
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Filing: 1974-09-12
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Granted: 1976-03-30
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Expires: 1994-09-12
Abstract
Abstract The disclosed synchronizing circuit employs flip-flops to synchronize a data signal to a clock pulse. The two flip-flops are controlled by the clock pulse and a delayed data signal to at least one of the flip-flops, the other flip-flop also being controlled by a delayed data signal or the data signal directly. A temporizing circuit receives the clock pulse and the output signal of one flip-flop and delivers a signal having a variable time delay according to the phase conditions between the data signal and the clock pulse. An AND gate or an appropriately connected JK flip-flop receives the output signal of the other flip-flop and the output signal of the temporizing circuit to provide the desired synchronized output pulse. This synchronizing circuit protects against the flip-flops synchronizing in an unstable state due to the critical period of the sampling edge of the clock pulse.
Inventors
- 👤 Michel J. M. Archer
- 👤 Henri-Claude L. Battut
- 👤 Robert R. C. Bonami
- 👤 Herve J. P. M. Louboutin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:51
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03L; H03L7/00; H03L7/02; H03L7/04; H03L7/24
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
322 words
An electronic synchronizing circuit employing two stable flip-flops to synchronize a data signal by a clock signal, said data signal having no fixed phase relation with said clock signal, ensuring the protection of a synchronized signal from an unstable state of said flip-flops comprising: a first source of said data signal; a second source of said clock signal; two flip-flops each having at least an output, a clock input coupled to said second source and a data input; at least one delay circuit having an input coupled to said first source and an output coupled to said data input of one of said two flip-flops to couple said data signal to said one of said two flip-flops after a first given time delay greater than a critical period of said two flip-flops; said data input of the other of said two flip-flops being coupled to said first source; a temporizing circuit having two inputs and an output, one of said two inputs of said temporizing circuit being coupled to said second source to receive said clock signal and the other of said two inputs of said temporizing circuit being coupled to said output of said one of said two flip-flops to receive the output signal of said one of said flip-flops to provide a control signal having a variable delay with respect to said clock signal according to the phase relation between said clock signal and said data signal; and a logic circuit having at least two inputs and an output, one of said two inputs of said logic circuit being coupled to said output of said temporizing circuit and the other of said two inputs of said logic circuit being coupled to said output of the other of said two flip-flops to provide a stable logical signal at said output of said logic circuit representing the output state of said other of said two flip-flops when said control signal is present.
Claim 2
Dependent Claim
322 words
An electronic synchronizing circuit employing two stable flip-flops to synchronize a data signal by a clock signal, said data signal having no fixed phase relation with said clock signal, ensuring the protection of a synchronized signal from an unstable state of said flip-flops comprising: a first source of said data signal; a second source of said clock signal; two flip-flops each having at least an output, a clock input coupled to said second source and a data input; at least one delay circuit having an input coupled to said first source and an output coupled to said data input of one of said two flip-flops to couple said data signal to said one of said two flip-flops after a first given time delay greater than a critical period of said two flip-flops; said data input of the other of said two flip-flops being coupled to said first source; a temporizing circuit having two inputs and an output, one of said two inputs of said temporizing circuit being coupled to said second source to receive said clock signal and the other of said two inputs of said temporizing circuit being coupled to said output of said one of said two flip-flops to receive the output signal of said one of said flip-flops to provide a control signal having a variable delay with respect to said clock signal according to the phase relation between said clock signal and said data signal; and a logic circuit having at least two inputs and an output, one of said two inputs of said logic circuit being coupled to said output of said temporizing circuit and the other of said two inputs of said logic circuit being coupled to said output of the other of said two flip-flops to provide a stable logical signal at said output of said logic circuit representing the output state of said other of said two flip-flops when said control signal is present.
Claim 3
Dependent Claim
14 words
A circuit according to claim 1, wherein said logic circuit being an AND gate.
Claim 4
Dependent Claim
14 words
A circuit according to claim 1, wherein said logic circuit being a JK-type flip-flop.
Claim 5
Dependent Claim
233 words
A circuit according to claim 1, wherein said temporizing circuit includes a third source of reference voltage; a capacitor having one terminal connected to ground; a voltage comparator coupled to said third source and the other terminal of said capacitor to compare the voltage across said capacitor with said reference voltage, the output of said comparator being connected to said one of said two inputs of said logic circuit, and changing logical state when the voltage across said capacitor equals said reference voltage; first means connected between said other terminal of said capacitor and said one of said two inputs of said temporizing circuit responsive to said clock signal to enable said voltage across said capacitor to change, after a second given time delay greater than said first given time delay, from a rest voltage to said reference voltage, and second means connected between said other terminal of said capacitor and said other of said two inputs of said temporizing circuit enabling said output signal of said one of said two flip-flops to change said voltage across said capacitor from said rest voltage to said reference voltage after a third given time delay less than said second given time delay when said output signal exists and is stable and after a fourth given time delay disposed between said second and third given time delays when said output signal is in an unstable state.
Claim 6
Dependent Claim
91 words
A circuit according to claim 4, wherein said first means provides a slow charging circuit for said capacitor and includes at least one resistor to receive said clock signal coupled between said one of said two inputs of said temporizing circuit and said other terminal of said capacitor; and said second means provides a fast charging circuit for said capacitor and includes a diode coupled to said other of said two inputs of said temporizing circuit, and a resistor in series with said diode and said other terminal of said capacitor.
Claim 7
Dependent Claim
174 words
A circuit according to claim 4, wherein said first means provides a slow discharge circuit for said capacitor and includes an inverter to receive said clock signal having an output and an input, said input of said inverter being coupled to said one of said two inputs of said temporizing circuit, at least one resistor in series between said output of said inverter and said other terminal of said capacitor, and a diode connected in parallel with said one resistor, said diode charging said capacitor in the absence of said clock signal; and said second means providing a fast discharge circuit for said capacitor and including a transistor control circuit having an input and an output, said input of said transistor control circuit being connected to said other of said two inputs of said temporizing circuit, and a switching transistor connected between said output of said transistor control circuit and said other terminal of said capacitor, said switching transistor being saturated by said transistor control circuit to permit a fast discharge of said capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-30 | 1979-09-29 | 1980-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-30 | 1983-09-29 | 1984-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-30 | 1987-09-29 | 1988-03-30 | $7700.00 | Window Closed / Lapsed |